Abstract: A method for manufacturing a semiconductor device, includes: forming a shallow trench isolation structure surrounding a first semiconductor fin and a second semiconductor fin; forming a dummy gate structure across the first and second semiconductor fins; forming a first flowable dielectric layer over the first and second semiconductor fins; curing the first flowable dielectric layer at a first temperature; removing a first portion of the cured first flowable dielectric layer from above the second semiconductor fin; after removing the first portion of the cured first flowable dielectric layer, forming a second flowable dielectric layer over the second semiconductor fin; curing the second flowable dielectric layer at a second temperature different from the first temperature; and replacing the dummy gate structure with a metal gate structure.

Abstract: Integrated circuit devices and methods of forming the same are provided. An integrated circuit device in an embodiment includes a first multi-gate active region over a substrate, a second multi-gate active region over the substrate, a first gate structure over the first multi-gate active region, a second gate structure over the second multi-gate active region, and a dielectric feature disposed between the first gate structure and the second gate structure. The dielectric feature includes an oxygen-free layer in contact with the first gate structure and the second gate structure, a silicon oxide layer over the oxygen-free layer, and a transition layer disposed between the oxygen-free layer and the silicon oxide layer. An oxygen content of the transition layer is smaller than an oxygen content of the silicon oxide layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a metal gate stack over the semiconductor substrate. The semiconductor device structure also includes a spacer element over a sidewall of the metal gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. An atomic concentration of the dopant decreases along a direction from an inner surface of the spacer element adjacent to the metal gate stack towards an outer surface of the spacer element.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Abstract: A semiconductor structure includes source/drain (S/D) features disposed over a semiconductor substrate, a metal gate stack disposed between the S/D features, where the metal gate stack traverses a channel region between the S/D features, gate spacers disposed on sidewalls of the metal gate stack, and an etch-stop layer (ESL) disposed over the gate spacers and the S/D features. The semiconductor structure further includes an oxide liner disposed on the ESL, where the oxide liner includes silicon oxide and silicon dioxide, and an interlayer dielectric (ILD) layer disposed on the oxide liner, where composition of the ILD layer is different from composition of the oxide liner.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: A dummy gate is formed over a substrate. A sacrificial layer is formed over the dummy gate. An interlayer dielectric (ILD) is formed over the dummy gate and over the sacrificial layer. The dummy gate is replaced with a metal-containing gate. The sacrificial layer is removed. A removal of the sacrificial layer leaves air gaps around the metal-containing gate. The air gaps are then sealed.

Abstract: Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate. The dummy gate stack has a dummy gate electrode and a dummy gate dielectric layer. The method also includes forming spacer elements over sidewalls of the dummy gate stack and partially removing the dummy gate electrode to form a recess. The method further includes partially removing the spacer elements to enlarge the recess and removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer. In addition, the method includes doping the spacer elements after the remaining portion of the dummy gate electrode is removed and removing the dummy gate dielectric layer. The method further includes forming a metal gate stack in the recess.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Abstract: Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate. The dummy gate stack has a dummy gate electrode and a dummy gate dielectric layer. The method also includes forming spacer elements over sidewalls of the dummy gate stack and partially removing the dummy gate electrode to form a recess. The method further includes partially removing the spacer elements to enlarge the recess and removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer. In addition, the method includes doping the spacer elements after the remaining portion of the dummy gate electrode is removed and removing the dummy gate dielectric layer. The method further includes forming a metal gate stack in the recess.

Abstract: A method includes forming a dummy gate structure over a substrate, forming a plurality of gate spacers respectively on opposite sidewalls of the dummy gate structure and having a first dielectric constant, removing the dummy gate structure to form a gate trench between the gate spacers, forming a dopant source layer to line the gate trench, annealing the dopant source layer to diffuse k-value reduction impurities from the dopant source layer into the gate spacers to lower the first dielectric constant of the gate spacers to a second dielectric constant, and forming a replacement gate stack in the gate trench.

Abstract: Aspects of the disclosure provide a method for fabricating a semiconductor device. A pre-stress liner is formed over a structure. The structure includes a gate structure having sidewalls. A protection layer is formed. The protection layer covers a first portion of the pre-stress liner that extends along the sidewalls of the gate structure, and exposes a second portion of the pre-stress liner that is away from the sidewalls of the gate structure. An oxygen-containing layer is formed. The oxygen-containing layer covers the pre-stress liner and the protection layer. The oxygen-containing layer is separated from the first portion of the pre-stress liner by the protection layer. The structure is annealed such that the second portion of the pre-stress liner oxidizes by receiving oxygen from the oxygen-containing layer, while the first portion of the pre-stress liner remains unoxidized due to the protection layer.

Abstract: Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: In accordance with the present invention, a structure of an asymmetric high-voltage MOS device is disclosed. The key aspect of the present invention is a high-voltage MOS device having a drift region underneath an isolation structure, wherein the high-voltage MOS device is isolated by shallow trench isolations and formed on a silicon-on-insulator (SOI) substrate. The asymmetric high-voltage MOS device comprises a substrate having an insulating layer thereon and a semiconductor layer of a first conductive type on the insulating layer. A plurality of shallow trench isolations defining an active area is formed in the semiconductor layer. A field oxide layer is formed in the active area of the semiconductor layer. A drift region of a second conductive type is formed under the field oxide layer in the semiconductor layer. A gate structure including a conductive layer and a gate dielectric layer is formed on the semiconductor layer in the active area and covers a portion of the field oxide layer.