Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

Abstract: A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.

Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

Abstract: A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.

Abstract: A scytovirin domain 1 (SD1) polypeptide, a nucleic acid encoding the polypeptide, and related fusion proteins, conjugates, isolated cells, vectors, and antibodies, as well as a method of inhibiting a viral infection using the same.

Abstract: An integrated circuit including a plurality of Fin field effect transistors (FINFETs) is provided. The integrated circuit includes a plurality of fin-channel bodies over a substrate. The fin-channel bodies include a first fin-channel body and a second fin-channel body. A gate structure is disposed over the fin-channel bodies. At least one first source/drain (S/D) region of a first FINFET is adjacent the first fin-channel body. At least one second source/drain (S/D) region of a second FINFET is adjacent the second fin-channel body. The at least one first S/D region is electrically coupled with the at least one second S/D region. The at least one first and second S/D regions are substantially free from including any fin structure.

Abstract: A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.

Abstract: A semiconductor device with an isolation feature is disclosed. The semiconductor device includes a plurality of gate structures disposed on a semiconductor substrate, a plurality of gate sidewall spacers of a dielectric material formed on respective sidewalls of the plurality of gate structures, an interlayer dielectric (ILD) disposed on the semiconductor substrate and the gate structures, an isolation feature embedded in the semiconductor substrate and extended to the ILD and a sidewall spacer of the dielectric material disposed on sidewalls of extended portion of the isolation feature.

Abstract: A liquid crystal display device includes a liquid crystal display panel having a gate line sequentially selected by a gate pulse and a plurality of light sources which are sequentially turned on along a scan direction of the gate line. The plurality of light sources are turned on with a first level of brightness during a white turn-on period, and turned on with a second level of brightness during a gray turn-on period. The second level of brightness is lower than the first level of brightness to irradiate the liquid crystal display panel with light. As a result, a life span of the plurality of light sources may be extended.

Abstract: There is provided an apparatus for measuring a warpage characteristic of a specimen, the apparatus including: a light irradiating unit irradiating light toward the specimen; alight transmitting member transmitting the light irradiated by the light irradiating unit therethrough and including a reference lattice pattern to allow a shadow to be formed on the specimen; a sensing unit sensing the shadow formed on the specimen by the reference lattice pattern; and a heating plate disposed under the light transmitting member and heating the specimen mounted thereon, wherein the reference lattice pattern formed on the light transmitting member is formed of a conductive material and is connected to a power supplying unit to thereby generate heat when power is supplied.

Abstract: Exemplary embodiments of the described technology relate generally to display devices including dye-sensitized solar cells. The display device according to an exemplary embodiment includes a display element for displaying an image, and a dye-sensitized solar cell for converting light into electricity to offset the power consumption of the display element. The dye-sensitized solar cell includes a selective photo-absorption material for selectively absorbing light from at least one wavelength band.

Abstract: Exemplary embodiments of the described technology relate generally to display devices including dye-sensitized solar cells. The display device according to an exemplary embodiment includes a display element for displaying an image, and a dye-sensitized solar cell for converting light into electricity to offset the power consumption of the display element. The dye-sensitized solar cell includes a selective photo-absorption material for selectively absorbing light from at least one wavelength band.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.

Abstract: An auto-focusing apparatus and method, the apparatus including an emission unit, the emission unit being configured to irradiate light on the organic light-emitting display apparatus; an optical system between the organic light-emitting display apparatus and the emission unit, the optical system being configured to adjust a position of the optical system on an optical axis and focus the irradiated light on the pixel unit; a light-receiving unit, the light-receiving unit being configured to receive light reflected by the organic light-emitting display apparatus and measure an intensity and a wavelength of the reflected light; and a controller, the controller being configured to receive the intensity of light measured by the light-receiving unit, control the position of the optical system, determine that the auto-focusing apparatus is focusing light onto the pixel unit when the intensity of light received by the light-receiving unit is a maximum value, and determine the position of the optical system as an opti

Abstract: A liquid crystal display panel capable of reducing a capacitance of a parasitic capacitor between a data line and a pixel electrode. The liquid crystal display panel comprises: a thin film transistor at a crossing of a gate line and a data line, liquid crystal cells including a pixel electrode connected to the thin film transistor; first shield patterns in the liquid crystal cells, each shield pattern being parallel to the data line without overlapping the data line, wherein the shield patterns are insulated from and overlap with an outer portion of the pixel electrode; and a common line arrayed to connect the shield patterns for each the liquid crystal cell.

Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.

Abstract: Disclosed herein are an apparatus and method for measuring characteristics of multi-layered thin films.