Patents by Inventor Chang Yun

Chang Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170271503
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Publication number: 20170271745
    Abstract: An antenna cover for an antenna of an aircraft includes a thermal barrier having an aerogel blanket having a shape of the antenna cover. The aerogel blanket has an inner side and an outer side with edges therebetween. The inner side is configured to face the antenna. The antenna cover includes a cover layer applied to the aerogel blanket. The cover layer includes at least one polytetrafluoroethylene (PTFE) sheet being a structurally reinforcing layer affixed to the outer side of the aerogel blanket to provide rigidity to the aerogel blanket.
    Type: Application
    Filed: March 17, 2016
    Publication date: September 21, 2017
    Inventors: Hyo Chang Yun, Kathleen Fasenfest, Thomas D. Ratzlaff, Lei Wang, Ismael L. Sandoval
  • Publication number: 20170245380
    Abstract: A thermal barrier for an electronic component includes an aerogel blanket configured to cover at least a portion of the electronic component and a cover positioned between the aerogel blanket and the electronic component. The aerogel blanket has a top, a bottom and edges therebetween. The bottom is configured to face the electronic component. The cover is a structurally reinforcing fabric affixed to the bottom of the aerogel blanket. The cover inhibits dust migration from the aerogel blanket toward the electronic component.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Inventors: Hyo Chang Yun, Thomas D. Ratzlaff, Ismael L. Sandoval, David A. Hurrell, Bruce R. Conway, Peter J. Dutton
  • Publication number: 20170226389
    Abstract: An adhesive arrangement includes an adhesive formed from an adhesive composition, the adhesive composition having a fluoropolymeric material, a functionalized fluoropolymeric material, and a thermoplastic material, and a base layer in contact with the adhesive, the base layer being a perfluoropolymeric material, a composite material, a metal material, or a metallic material. The thermoplastic material is selected from the group consisting of polyamide (PA), polyphenylenesulfide (PPS), polyetheretherketone (PEEK), polyimide (PI), polyimide derivatives such as polyetherimide (PEI), polyaryletherketone (PAEK), polyaryletherketone derivatives, polysulfone, polyethersulfone (PES), polysulfone derivatives, and combinations thereof.
    Type: Application
    Filed: February 10, 2016
    Publication date: August 10, 2017
    Applicant: Tyco Electronics Corporation
    Inventors: Lei Wang, Hyo Chang Yun, Peter J. Dutton
  • Patent number: 9711412
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Munufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Patent number: 9673328
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Publication number: 20170117388
    Abstract: An exemplary method of forming a fin field effect transistor that includes first and second etching processes to form a fin structure. The fin structure includes an upper portion and a lower portion separated at a transition. The upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 27, 2017
    Inventors: Feng YUAN, Hung-Ming CHEN, Tsung-Lin LEE, Chang-Yun CHANG, Clement Hsingjen WANN
  • Publication number: 20170018641
    Abstract: FinFET devices, along with methods for fabricating such devices, are disclosed herein for facilitating device characterization. An exemplary FinFET device includes a fin having a first portion extending in a first direction and a second portion extending from the first portion in a second direction. The second direction is substantially perpendicular to the first direction. The first portion includes a first region doped with a first type dopant disposed between second regions doped with a second type dopant. The first type dopant is opposite the second type dopant. A source contact and a drain contact are coupled to the second regions of the first portion, and a body contact is coupled to the second portion. A gate is disposed over the first region of the first portion, and the second portion extends from the first region.
    Type: Application
    Filed: September 27, 2016
    Publication date: January 19, 2017
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Cheng-Chuan Huang, Fu-Liang Yang
  • Publication number: 20160358926
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Publication number: 20160333060
    Abstract: An isolated and purified nucleic acid molecule that encodes a polypeptide comprising at least eight contiguous amino acids of SEQ ID NO: 1, 2, or 3, wherein the at least eight contiguous amino acids have anti-viral activity, as well as an isolated and purified nucleic acid molecule that encodes a polypeptide comprising at least eight contiguous amino acids of SEQ ID NO: 1, 2, or 3, wherein the at least eight contiguous amino acids have anti-viral activity, a vector comprising such an isolated and purified nucleic acid molecule, a host cell comprising the nucleic acid molecule, optionally in the form of a vector, a method of producing an antiviral polypeptide or conjugate thereof, the anti-viral polypeptide itself, a conjugate or fusion protein comprising the anti-viral polypeptide, and compositions comprising an effective amount of the anti-viral polypeptide or conjugate or fusion protein thereof. Further provided are methods of inhibiting prophylactically or therapeutically a viral infection of a host.
    Type: Application
    Filed: January 9, 2015
    Publication date: November 17, 2016
    Applicant: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY, DEPARTMENT OF HEALTH AND HUMAN SER . . .
    Inventors: Barry R. O'Keefe, James B. McMahon, Koreen Ramessar, Chang-yun Xiong
  • Patent number: 9484462
    Abstract: An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: November 1, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Yuan, Hung-Ming Chen, Tsung-Lin Lee, Chang-Yun Chang, Clement Hsingjen Wann
  • Publication number: 20160284600
    Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Inventors: Jhon-Jhy Liaw, Chang-Yun Chang
  • Patent number: 9455348
    Abstract: A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Cheng-Chuan Huang, Fu-Liang Yang
  • Publication number: 20160268016
    Abstract: Static dissipative articles and processes of producing static dissipative articles are described. The static dissipative article includes a conductor and a dissipative coating over the conductor, the dissipative coating including a polymer matrix and between 0.1 and 10%, by weight, conductive nano-carbons homogenously distributed with the polymer matrix. The dissipative coating has a resistivity of between 106 and 1014 ohm·cm, and the conductive-nano-carbons have an aspect ratio of at least 100. The process of producing a coated article includes blending a polymer powder with between 0.1 and 10%, by weight, conductive nano-carbons to form a micron-level homogenous compound, and extruding the compound onto a conductor to form a dissipative coating over the conductor.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 15, 2016
    Applicant: Tyco Electronics Corporation
    Inventors: Hyo Chang Yun, Lei Wang, Peter J. Dutton
  • Patent number: 9425102
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Publication number: 20160240675
    Abstract: A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 9392708
    Abstract: An enclosure includes a plurality of modular construction units that connect together to at least partially define an internal compartment of the enclosure. Each construction unit includes a wall segment extending a length from a corner end to a free end, and a corner segment extending outward from the corner end of the wall segment. The corner segment is integrally formed with the wall segment. The corner segment includes a receiver socket that is configured to receive the free end of another corresponding construction unit therein to connect the construction units together. The construction units connect together one after the other with a chasing symmetry to define the internal compartment of the enclosure.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: July 12, 2016
    Assignee: TYCO ELECTRONICS CORPORATION
    Inventors: Bruce R. Conway, Hyo Chang Yun, Peter J. Dutton, Thomas D. Ratzlaff, Paul Craig Tally, James O'Keeffe, Erling Hansen
  • Patent number: 9382038
    Abstract: An enclosure includes a plurality of modular corner segments and a plurality of modular wall segments that connect together to at least partially define an internal compartment of the enclosure. The wall segments extending lengths between opposite free ends. At least a majority of the wall segments are fabricated from a polymer. Each corner segment includes opposite first and second receiver sockets that are each configured to receive a corresponding free end of a corresponding wall segment therein to connect the corner segment to the corresponding wall segments. At least a majority of the corner segments are fabricated from a polymer. The corner segments and the wall segments connect together to define the internal compartment of the enclosure.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: July 5, 2016
    Assignee: TYCO ELECTRONICS CORPORATION
    Inventors: Bruce R. Conway, Hyo Chang Yun, Peter J. Dutton, Thomas D. Ratzlaff, Paul Craig Tally, James O'Keeffe, Erling Hansen
  • Publication number: 20160163851
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 9, 2016
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Publication number: 20160160090
    Abstract: An adhesive arrangement includes an adhesive formed from an adhesive composition having a thermoplastic material and a melt-processable perfluoropolymeric material. The adhesive arrangement further includes a base layer in contact with the adhesive. The thermoplastic material is polyetherimide (PEI), polyphenylenesulfide (PPS), polyaryletherketone (PAEK) including polyetheretherketone (PEEK), polyamide (PA), and/or polysulfone derivatives including polysulfone. The base layer is a perfluoropolymeric material, a composite material, a metal material, a metallic material, another suitable material, or a combination thereof.
    Type: Application
    Filed: December 4, 2014
    Publication date: June 9, 2016
    Applicant: Tyco Electronics Corporation
    Inventors: Lei Wang, Hyo Chang Yun, Peter J. Dutton