Patents by Inventor Chang Yun

Chang Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell layout
    Patent number: 9362290
    Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhon-Jhy Liaw, Chang-Yun Chang
  • Substrate treating apparatus and blocker plate assembly
    Patent number: 9362091
    Abstract: A substrate treating apparatus includes a chamber that encloses an internal space; a susceptor in a lower part of the internal space; a shower head in an upper part of the internal space and spaced above the susceptor and that includes a plurality of distribution holes; and a blocker plate assembly that comprises a body having a plurality of intake holes that divides a space between a top wall of the chamber and the shower head into an upper intake space and a lower distribution space, a ring-shaped partition rib on an upper surface of the body, and a ring-shaped distribution unit on a lower surface of the body.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: June 7, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soyoung Lee, Suho Lee, Chang-Yun Lee, Ik Soo Kim, Juhyun Lee, Jongwon Hong
  • Driving circuit for display device and method of driving the same
    Patent number: 9330618
    Abstract: A driving circuit for a display device, for reducing power consumption of a data driver, and a method of driving the driving circuit are disclosed. The driving circuit includes a data driver for maintaining buffers of the data driver in an on state every preset specific frame period and maintaining the buffers in an off state every remaining period except for specific frame periods in a refresh mode for processing image data of one image for the specific frame periods only.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: May 3, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Sai-Chang Yun, You-Sung Nam, Si-Hyun Kim, Nak-Yoon Kim
  • Structure and method for transistor with line end extension
    Patent number: 9324866
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Semiconductor device and method for making the same using semiconductor fin density design rules
    Patent number: 9245080
    Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang
  • Modular Enclosure
    Publication number: 20150289389
    Abstract: An enclosure includes a plurality of modular corner segments and a plurality of modular wall segments that connect together to at least partially define an internal compartment of the enclosure. The wall segments extending lengths between opposite free ends. At least a majority of the wall segments are fabricated from a polymer. Each corner segment includes opposite first and second receiver sockets that are each configured to receive a corresponding free end of a corresponding wall segment therein to connect the corner segment to the corresponding wall segments. At least a majority of the corner segments are fabricated from a polymer. The corner segments and the wall segments connect together to define the internal compartment of the enclosure.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 8, 2015
    Applicant: Tyco Electronics Corporation
    Inventors: Bruce R. Conway, Hyo Chang Yun, Peter J. Dutton, Thomas D. Ratzlaff, Paul Craig Tally, James O'Keeffe, Erling Hansen
  • Modular Enclosure
    Publication number: 20150289388
    Abstract: An enclosure includes a plurality of modular construction units that connect together to at least partially define an internal compartment of the enclosure. Each construction unit comprises a wall segment extending a length from a corner end to a free end, and a corner segment extending outward from the corner end of the wall segment. The corner segment is integrally formed with the wall segment. The corner segment includes a receiver socket that is configured to receive the free end of another corresponding construction unit therein to connect the construction units together. The construction units connect together one after the other with a chasing symmetry to define the internal compartment of the enclosure.
    Type: Application
    Filed: April 4, 2014
    Publication date: October 8, 2015
    Applicant: Tyco Electronics Corporation
    Inventors: Bruce R. Conway, Hyo Chang Yun, Peter J. Dutton, Thomas D. Ratzlaff, Paul Craig Tally, James O'Keeffe, Erling Hansen
  • SUBSTRATE TREATING APPARATUS AND BLOCKER PLATE ASSEMBLY
    Publication number: 20150167705
    Abstract: A substrate treating apparatus includes a chamber that encloses an internal space; a susceptor in a lower part of the internal space; a shower head in an upper part of the internal space and spaced above the susceptor and that includes a plurality of distribution holes; and a blocker plate assembly that comprises a body having a plurality of intake holes that divides a space between a top wall of the chamber and the shower head into an upper intake space and a lower distribution space, a ring-shaped partition rib on an upper surface of the body, and a ring-shaped distribution unit on a lower surface of the body.
    Type: Application
    Filed: August 19, 2014
    Publication date: June 18, 2015
    Inventors: SOYOUNG LEE, SUHO LEE, CHANG-YUN LEE, IKSOO KIM, JUHYUN LEE, JONGWON HONG
  • STRUCTURE AND METHOD FOR PROVIDING LINE END EXTENSIONS FOR FIN-TYPE ACTIVE REGIONS
    Publication number: 20150115373
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 30, 2015
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • FinFETs with Different Fin Heights
    Publication number: 20150111355
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Application
    Filed: January 7, 2015
    Publication date: April 23, 2015
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Adhesive Composition and Article
    Publication number: 20150056443
    Abstract: An adhesive composition blend and an article are disclosed. The adhesive composition blend includes a higher-melt fluoropolymer component having a melting point greater than a predetermined maximum service temperature and a lower-melt fluoropolymer component having a melting point less than a predetermined applying temperature. The melting point of the higher-melt fluoropolymer is at least 20° C. greater than the melting point of the lower-melt fluoropolymer. Additionally or alternatively, the adhesive composition blend includes a higher-melt fluoropolymer component having a melting point between about 200° C. and about 330° C. and a lower-melt fluoropolymer component having a melting point between about 100° C. and about 260° C. The article includes a substrate and the adhesive.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: Tyco Electronics Corporation
    Inventors: Lei Wang, Hyo Chang Yun, David A. Hurrell
  • Adhesive Manufacturing Process, an Adhesive, and an Article
    Publication number: 20150056444
    Abstract: An adhesive manufacturing process, an adhesive, and an article are disclosed. The adhesive manufacturing process includes blending a lower-melt fluoropolymer having a melting point that is less than a first temperature with a fluoropolymer powder having a melting point that is greater than a second temperature to form an adhesive and applying the adhesive to a surface at the first temperature. The adhesive is configured to be exposed to the second temperature. The adhesive includes the lower-melt fluoropolymer and the fluoropolymer powder blended with the lower-melt fluoropolymer. The article includes a surface and the adhesive applied to the surface at an applying temperature.
    Type: Application
    Filed: August 26, 2013
    Publication date: February 26, 2015
    Applicant: Tyco Electronics Corporation
    Inventors: Lei Wang, Hyo Chang Yun
  • FinFETs with different fin heights
    Patent number: 8941153
    Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
  • Display panel test apparatus and method thereof
    Patent number: 8922600
    Abstract: A display panel test apparatus that may include: a first measurer measuring first R, G, and B components of light emitted from a display panel at a first viewing angle; a second measurer measuring second R, G, and B components of light emitted from the display panel at a second viewing angle; a color coordinate calculator calculating a first xy color coordinate at the first viewing angle using the first R, G, and B components and calculating a second xy color coordinate at the second viewing angle using the second R, G, and B components; and a panel controller compensating a target color coordinate of the display panel to include the first xy color coordinate and the second xy color coordinate into a specification area on a color coordinate system.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: December 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang-Yun Moon, Hee-Seong Jeong, Won-Ju Shin
  • SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME USING SEMICONDUCTOR FIN DENSITY DESIGN RULES
    Publication number: 20140331192
    Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 6, 2014
    Inventors: Shao-Ming YU, Chang-Yun CHANG
  • High gate density devices and methods
    Patent number: 8871597
    Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming sidewall spacers on sidewalls of the dummy gate structures and forming a plurality of epitaxial growth regions between the dummy gate structures. After forming the plurality of epitaxial growth regions, one of the dummy gate structures is removed to form an isolation trench, which is filled with a dielectric layer to form an isolation feature. The remaining dummy gate structures are removed to form gate trenches, and gate structures are formed in the gate trenches.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Chang-Yun Chang, Hsin-Chih Chen
  • Fully depleted SOI multiple threshold voltage application
    Patent number: 8865539
    Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
  • DRIVING CIRCUIT FOR DISPLAY DEVICE AND METHOD OF DRIVING THE SAME
    Publication number: 20140306872
    Abstract: A driving circuit for a display device, for reducing power consumption of a data driver, and a method of driving the driving circuit are disclosed. The driving circuit includes a data driver for maintaining buffers of the data driver in an on state every preset specific frame period and maintaining the buffers in an off state every remaining period except for specific frame periods in a refresh mode for processing image data of one image for the specific frame periods only.
    Type: Application
    Filed: October 14, 2013
    Publication date: October 16, 2014
    Applicant: LG DISPLAY CO., LTD.
    Inventors: Sai-Chang YUN, You-Sung NAM, Si-Hyun KIM, Nak-Yoon KIM
  • Structure for a multiple-gate FET device and a method for its fabrication
    Patent number: RE45180
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
  • Structure for a multiple-gate FET device and a method for its fabrication
    Patent number: RE45944
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuang Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang