Abstract: A method includes providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction; epitaxially growing semiconductor source/drain (S/D) features over the first and second fins, wherein a first semiconductor S/D feature over the first fin merges with a second semiconductor S/D feature over the second fin; and performing a first etching process to an area between the first and second fins, wherein the first etching process separates the first and second semiconductor S/D features.

Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer in the first trench; and filling the first trench with a dielectric feature.

Abstract: A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.

Abstract: A device that includes a substrate; semiconductor fins extending from the substrate; an isolation structure over the substrate and laterally between the semiconductor fins; a liner layer between sidewalls of the semiconductor fins and the isolation structure; and an etch stop layer between the substrate and the isolation structure and laterally between the semiconductor fins. The etch stop layer includes a material different than that of the isolation structure and the liner layer.

Abstract: A method of inspecting a semiconductor substrate includes measuring light intensity of light reflected on the rotating semiconductor substrate, analyzing a frequency distribution of the measured light intensity, and determining a state of the semiconductor substrate by using the frequency distribution. The analyzing of the frequency distribution of the measured light intensity includes extracting a plurality of frequency components corresponding respectively to a plurality of frequencies from the measured light intensity.

Abstract: Provided are a deposition process monitoring system capable of detecting an internal state of a chamber in a deposition process, and a method of controlling the deposition process and a method of fabricating a semiconductor device using the system.

Abstract: FinFET devices, along with methods for fabricating such devices, are disclosed herein for facilitating device characterization. An exemplary FinFET device includes a fin having a first portion extending in a first direction and a second portion extending from the first portion in a second direction. The second direction is substantially perpendicular to the first direction. The first portion includes a first region doped with a first type dopant disposed between second regions doped with a second type dopant. The first type dopant is opposite the second type dopant. A source contact and a drain contact are coupled to the second regions of the first portion, and a body contact is coupled to the second portion. A gate is disposed over the first region of the first portion, and the second portion extends from the first region.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Abstract: An electrical device includes first and second terminals and a terminal holder holding the first and second terminals. A first insulation layer is provided between the first and second terminals and a second insulation layer is provided between the first and second terminals. The first and second insulation layers are different materials. The first insulation layer is a base layer and the second insulation layer is a high arc tracking resistance rated layer on the base layer to discourage arc tracking on the first insulation layer.

Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.

Abstract: A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.

Abstract: Provided are a deposition process monitoring system capable of detecting an internal state of a chamber in a deposition process, and a method of controlling the deposition process and a method of fabricating a semiconductor device using the system.

Abstract: An electrical device includes first and second terminals and a terminal holder holding the first and second terminals. A first insulation layer is provided between the first and second terminals and a second insulation layer is provided between the first and second terminals. The first and second insulation layers are different materials. The first insulation layer is a base layer and the second insulation layer is a high arc tracking resistance rated layer on the base layer to discourage arc tracking on the first insulation layer.

Abstract: An antenna cover for an antenna of an aircraft includes a thermal barrier having an aerogel blanket having a shape of the antenna cover. The aerogel blanket has an inner side and an outer side with edges therebetween. The inner side is configured to face the antenna. The antenna cover includes a cover layer applied to the aerogel blanket. The cover layer includes at least one polytetrafluoroethylene (PTFE) sheet being a structurally reinforcing layer affixed to the outer side of the aerogel blanket to provide rigidity to the aerogel blanket.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A thermal barrier for an electronic component includes an aerogel blanket configured to cover at least a portion of the electronic component and a cover positioned between the aerogel blanket and the electronic component. The aerogel blanket has a top, a bottom and edges therebetween. The bottom is configured to face the electronic component. The cover is a structurally reinforcing fabric affixed to the bottom of the aerogel blanket. The cover inhibits dust migration from the aerogel blanket toward the electronic component.

Abstract: An adhesive arrangement includes an adhesive formed from an adhesive composition, the adhesive composition having a fluoropolymeric material, a functionalized fluoropolymeric material, and a thermoplastic material, and a base layer in contact with the adhesive, the base layer being a perfluoropolymeric material, a composite material, a metal material, or a metallic material. The thermoplastic material is selected from the group consisting of polyamide (PA), polyphenylenesulfide (PPS), polyetheretherketone (PEEK), polyimide (PI), polyimide derivatives such as polyetherimide (PEI), polyaryletherketone (PAEK), polyaryletherketone derivatives, polysulfone, polyethersulfone (PES), polysulfone derivatives, and combinations thereof.

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: An exemplary method of forming a fin field effect transistor that includes first and second etching processes to form a fin structure. The fin structure includes an upper portion and a lower portion separated at a transition. The upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.