Abstract: Self-aligned semiconductor FET device source and drain contacts and techniques for formation thereof are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source and drains; lower source and drain contacts disposed on the source and drains; upper source and drain contacts disposed on the lower source and drain contacts; and a silicide present between the lower source and drain contacts and the upper source and drain contacts.

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the plurality of gate structures. In the method, a germanium oxide layer is formed on the plurality of gate structures and on the plurality of source/drain regions, and portions of the germanium oxide layer on the plurality of source/drain regions are converted into a plurality of dielectric layers. The method also includes removing unconverted portions of the germanium oxide layer from the plurality of gate structures, and depositing a plurality of cap layers in place of the removed unconverted portions of the germanium oxide layer. The plurality of dielectric layers are removed, and a plurality of source/drain contacts are formed on the plurality of source/drain regions. The plurality of source/drain contacts are adjacent the plurality of cap layers.

Abstract: A method includes forming a first metallization layer on a substrate comprising a plurality of conductive lines. The method further includes forming a first dielectric layer on the substrate and between adjacent conductive lines. The method further includes forming a first via layer comprising at least one via in the first dielectric layer and exposing a top surface of at least one of the plurality of conductive lines. The method further includes depositing a first conductive material in the first via. The method further includes forming a barrier layer on a top surface of the first dielectric layer and exposing a top surface of the plurality of conductive lines and the first conductive material.

Abstract: An interconnect structure includes a first electrically conductive via portion on an upper surface of a substrate, the first electrically conductive via elongated along a first direction, and a first ILD material on the substrate and covering the first electrically conductive via portion. The first ILD material includes an ILD upper surface exposing a via surface of the first electrically conductive via portion. A second electrically conductive via portion is on the ILD upper surface and the via upper surface thereby defining a contact area between the first electrically conductive via portion and the second electrically conductive via portion. The second electrically conductive via portion elongated along a second direction orthogonal with respect to the first direction. A second ILD material is on the ILD upper surface to cover the second electrically conductive via portion. The first and second electrically conductive via portions are fully aligned at the contact area.

Abstract: Methods and structures for pitch multiplication include forming a plurality of mandrel lines and non-mandrel lines on a target layer, wherein the non-mandrel lines include a protective spacer material about a top sidewall portion and a first spacer material about a lower sidewall portion, wherein the protective spacer material has a different etch selectivity than the first spacer material. The plurality of mandrel lines and non-mandrel lines are transferred into the target layer.

Abstract: A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, SD, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, GD. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer.

Abstract: A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.

Abstract: A method includes forming a stacked nanosheet structure on a semiconductor substrate. The stacked nanosheet structure includes a plurality of alternating sacrificial nanosheets and channel nanosheets. The method further includes forming a dummy gate structure about the stacked nanosheet structure. The method also includes removing outer surface regions of the sacrificial nanosheets to define an at least partial recess at each outer surface region and forming an inner spacer within each of the at least partial recesses. The method also includes forming an isolation layer adjacent at least outer surface regions of at least the channel nanosheets. The method further includes forming a source region and a drain region about the stacked nanosheet structure. The method also includes removing the sacrificial nanosheets through an etching process whereby the isolation layer and the inner spacers isolates the source and drain regions from the etching process.

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a semiconductor fin and a liner in contact with end portions of the semiconductor fin. A first source/drain contacts the liner and sidewalls of the semiconductor fin. A gate structure is in contact with and surrounds the semiconductor fin. A second source/drain is formed above the first source/drain. The method includes forming, on a substrate, at least one semiconductor fin having a first spacer in contact with an upper portion of the semiconductor fin, and a second spacer in contact with the first spacer and a lower portion of the semiconductor fin. The semiconductor fin is patterned into a plurality of semiconductor fins. A liner is formed on exposed end portions of each semiconductor fin of the plurality of semiconductor fins.

Abstract: Integrated circuits include back end of line metallization levels. An upper metallization level is on a lower metallization level and includes at least one top via-line interconnect structure in an interlayer dielectric. The lower metallization level includes at least one top via-line interconnect structure in an interlayer dielectric, wherein the top via is raised relative to the interlayer dielectric in the lower metallization level. The line in the upper metallization level contacts a top surface and sidewall portions of the top via raised above the interlevel dielectric. Also described are methods for fabricating the same.

Abstract: Scalable device designs for FINFET technology are provided. In one aspect, a method of forming a FINFET device includes: patterning fins in a substrate which include a first fin(s) corresponding to a first FINFET device and a second fin(s) corresponding to a second FINFET device; depositing a conformal gate dielectric over the fins; depositing a conformal sacrificial layer over the gate dielectric; depositing a sacrificial gate material over the sacrificial layer; replacing the sacrificial layer with a first workfunction-setting metal(s) over the first fin(s) and a second workfunction-setting metal(s) over the second fin(s); removing the sacrificial gate material; forming dielectric gates over the first workfunction-setting metal(s), the second workfunction-setting metal(s) and the gate dielectric forming gate stacks; and forming source and drains in the fins between the gate stacks, wherein the source and drains are separated from the gate stacks by inner spacers. A FINFET device is also provided.

Abstract: A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor laser and a BRS operating as a reversible switch. The BRS operates in a high resistive state in which a semiconductor laser is below a lasing threshold and emitting in a reduced spontaneous emission regime, and a low resistive state in which a semiconductor laser is above or equal to a lasing threshold and emitting in a stimulated emission regime. The BRS operating as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using insulator-to-metal transition (IMT) materials or is formed using threshold-switching selectors (TSS).

Abstract: A back end of line interconnect structure and methods for forming the interconnect structure including a fully aligned via design generally includes wide lines formed of copper and narrow lines formed of an alternative metal. The fully aligned vias are fabricated using a metal recess approach and the hybrid metal conductors can be fabricated using a selective deposition approach.

Abstract: A method for manufacturing a semiconductor device includes forming an interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. A trench and an opening are formed in the third and second dielectric layers, respectively. A barrier layer is deposited in the trench and in the opening, and on a top surface of the interconnect. The method also includes removing the barrier layer from the top surface of the interconnect and from a bottom surface of the trench, and depositing a conductive fill layer in the trench and in the opening, and on the interconnect. A bottom surface of the trench includes the etch stop layer.

Abstract: A method for fabricating a semiconductor device includes selectively etching one or more of a plurality of conductive layers within a metallization level to obtain one or more recessed conductive layers each corresponding to a conductive line lacking a via disposed thereon and at least one conductive line having a via disposed thereon. The metallization level is disposed on a base structure including one or more underlying devices. The method further includes forming a pair of planarization stop layers on each of the one or more recessed conductive layers to a height of the via, and forming a plurality of interlevel dielectric (ILD) layers having a uniform height across the metallization level using the one or more pairs of planarization stop layers.

Abstract: A method for fabricating a semiconductor device includes selectively etching one or more of a plurality of conductive layers within a metallization level to obtain one or more recessed conductive layers each corresponding to a conductive line lacking a via disposed thereon and at least one conductive line having a via disposed thereon. The metallization level is disposed on a base structure including one or more underlying devices. The method further includes forming a pair of planarization stop layers on each of the one or more recessed conductive layers to a height of the via, and forming a plurality of interlevel dielectric (ILD) layers having a uniform height across the metallization level using the one or more pairs of planarization stop layers.

Abstract: A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of interconnects spaced apart from each other on a substrate. The plurality of interconnects each have an upper portion and a lower portion. In the method, a plurality of spacers are formed on sides of the upper portions of the plurality of interconnects. A space is formed between adjacent spacers of the plurality of spacers on adjacent interconnects of the plurality of interconnects. The method also includes forming a dielectric layer on the plurality of spacers and on the plurality of interconnects. The dielectric layer fills in the space between the adjacent spacers of the plurality of spacers, which blocks formation of the dielectric layer in an area below the space. The area below the space is between lower portions of the adjacent interconnects.