Abstract: A semiconductor structure includes a field effect transistor (FET) having a source/drain, a contact in contact with the source/drain, and a buried power rail including a conductive material, wherein the buried power rail is in contact with the contact, wherein a first portion of the buried power rail closest to the contact has a first thickness, and wherein a second portion of the buried power rail has a second thickness such that the first thickness is less than the second thickness.

Abstract: An etch stop layer is located on top of a first dielectric layer. A conductive line is located on top of the etch stop layer. A second dielectric layer is located above the first dielectric layer. The second dialect layer is in contact with the first dielectric layer.

Abstract: A phase change memory (PCM) structure including a bottom electrode, a first dielectric spacer disposed above and in contact with the bottom electrode, the first dielectric spacer comprising a vertical seam, a PCM layer disposed above the first dielectric spacer, and a heater element disposed in the seam and in contact with the bottom electrode.

Abstract: A semiconductor device includes a gate structure that is formed upon and around a channel fin. The device further includes a source or drain (S/D) region connected to the fin. A spacer liner is located upon a sidewall of the S/D region facing the gate structure. An air-gap spacer is located between the gate structure and the spacer liner. A spacer ear is located above the air-gap spacer between the gate structure and the spacer liner. The spacer ear may be formed by initially forming an inner spacer upon a sidewall of the gate structure and forming an outer spacer upon the inner spacer. The outer spacer may be recessed below the inner spacer and the spacer ear may be formed upon the recessed outer spacer. Subsequently, the inner spacer and outer spacer may be removed to form the air-gap spacer while retaining the spacer ear.

Abstract: A method of forming interconnects is provided. The method includes forming a plurality of mandrels on an interlayer dielectric (ILD) layer. The method further includes forming sidewall spacers on opposite sides of the each mandrel, wherein a portion of the ILD layer is exposed between adjacent sidewall spacers on adjacent mandrels, and removing the exposed portions of the ILD layer to form a first set of trenches between adjacent sidewall spacers. The method further includes forming a first set of interconnects in the first set of trenches, and removing the mandrels to expose portions of the ILD layer between the sidewall spacers. The method further includes removing the exposed portions of the ILD layer to form a second set of trenches between the sidewall spacers, and forming a second set of interconnects in the second set of trenches.

Abstract: A semiconductor structure includes a substrate, a first device disposed on the substrate and a second device disposed on the substrate. The first device includes a first plurality of nanosheets comprising a p-type material. The second device includes a second plurality of nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first device and the second device.

Abstract: A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Abstract: Interconnect structures including super vias are formed during back-end-of-line processing using sacrificial placeholders to protect the bottom portions of the super vias while upper portions of the super vias are formed. The sacrificial placeholders are removed and replaced by metal conductors that fill the bottom and upper portions of the super vias.

Abstract: A memory cell and formation thereof. The memory cell including: a first dielectric material having a via; a dielectric spacer on a sidewall of the via, and a second dielectric material pinching off the via and forming a seam.

Abstract: A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the first source/drain region comprises a smaller cross-section than the second source/drain region, a first dielectric material disposed in contact with a bottom surface and vertical surfaces of the first source/drain region and further in contact with a vertical surface and top surface of the second source/drain region, and a second dielectric material disposed as an interlayer dielectric material encapsulating the first and second transistors.

Abstract: An embodiment includes a method of forming a semiconductor device and the resulting device. The method may include forming a source/drain on an exposed portion of a semiconductor layer of a layered nanosheet. The method may include forming a sacrificial material on the source/drain. The method may include forming a dielectric layer covering the sacrificial material. The method may include replacing the sacrificial material with a contact liner. The semiconductor device may include a first gate nanosheet stack and second gate nanosheet stack. The semiconductor device may include a first source/drain in contact with the first nanosheet stack and a second source/drain in contact with the second nanosheet stack. The semiconductor device may include a source/drain dielectric located between the first source/drain and the second source/drain. The semiconductor device may include a contact liner in contact with the first source/drain, the second source/drain and the source/drain dielectric.

Abstract: Techniques for recovering the width of a top gate spacer in a field-effect transistor (FET) device are provided. In one aspect, a FET device includes: at least one gate; source/drain regions present on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source/drain regions, wherein each of the gate spacers includes an L-shaped spacer alongside the at least one gate and a dielectric liner disposed on the L-shaped spacer; and at least one channel interconnecting the source/drain regions. A method of forming a FET device is also provided which includes recovering the width of the top gate spacer using the dielectric liner.

Abstract: Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.

Abstract: A cross-couple contact structure is provided that is located on, and physically contacts, a topmost surface of a functional gate structure that is located laterally adjacent to a gate cut region. The cross-couple contact structure extends into the laterally adjacent gate cut region and physically contacts a sidewall of the functional gate structure, an upper portion of a first sidewall of a dielectric plug that is present in the gate cut region, and an upper surface of a dielectric liner that is located on a lower portion of the first sidewall of the dielectric plug.

Abstract: A multiple gate dielectrics and dual work-functions field effect transistor (MGO-DWF-FET) is provided on an active region of a semiconductor substrate. The MGO-DWF-FET includes a first functional gate structure including a U-shaped first high-k gate dielectric material layer and a first work-function metal-containing structure, and a laterally adjacent, and contacting, second functional gate structure that includes a U-shaped second high-k gate dielectric material layer and a second work-function metal-containing structure. The first functional gate structure has a gate length that differs from a gate length of the second functional gate structure.

Abstract: A top cap layer covering a first metal line and a second metal line, horizontally between the first metal line and the second metal line is, in sequential order, a post cap liner, an air gap and the post cap liner. A first set of metal lines embedded in an upper surface of a dielectric, a second set of metal lines embedded below the dielectric and above the electronic components, a post cap liner covering the first set of metal lines, a cavity which dissects a first metal line of the first set of metal lines and extends to a second metal line of the second set of metal lines and dissects the second set of metal lines. Forming a cavity in a first metal line embedded in an upper surface of a dielectric, where the first metal line and the dielectric are covered by a top cap layer.

Abstract: A semiconductor structure may include a first nanosheet field-effect transistor formed on a first portion of a substrate, a second nanosheet field-effect transistor formed on a second portion of the substrate, and one or more metal contacts. The first field-effect transistor formed on the first portion of a substrate may include a first source drain epitaxy. A top surface of the first source drain epitaxy may be above a top surface of a top-most nanosheet channel layer. The second nanosheet field-effect transistor formed on the second portion of the substrate may include a second source drain epitaxy and a third source drain epitaxy. The second source drain epitaxy may be below the third source drain epitaxy. The third source drain epitaxy may be u-shaped and may be connected to at least one nanosheet channel layer.

Abstract: An apparatus comprising a substrate and a thin gate oxide nanosheet device located on the substrate, having a first plurality of nanosheet layers, wherein each of the first plurality of nanosheet layers has a first thickness located at the center of the nanosheet. A thick gate oxide nanosheet device located on the substrate, having a second plurality of nanosheet layers, wherein each of the second plurality of nanosheet layers has a second thickness and wherein the first thickness is less than the second thickness.

Abstract: An embodiment of the invention may include a forkFET semiconductor structure, and the method of forming said structure. The structure may include a first FET device and a second FET device separated by a vertical dielectric pillar. The first FET device may include a first plurality of horizontal sheet channels. The second FET device may include a second plurality of horizontal sheet channels. The first plurality of horizontal sheet channels contains more horizontal sheets than the second plurality of horizontal sheet channels. This may enable adjustment of Weff for different devices on different sides of the pillar or different thicknesses of dielectrics used for the device.

Abstract: A semiconductor structure may include a metal line, a via above and in electrical contact with the metal lines, and a dielectric layer positioned along a top surface of the metal lines. A top surface of the dielectric layer may be below the dome shaped tip of the via. A top portion of the via may include a dome shaped tip. The semiconductor structure may include a liner positioned along the top surface of the dielectric layer and a top surface of the dome shaped tip of the via. The liner may be made of tantalum nitride or titanium nitride. The dielectric layer may be made of a low-k material. The metal line and the via may be made of ruthenium. The metal line may be made of molybdenum.