Abstract: A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.

Abstract: A method is presented for back-end-of-the-line (BEOL) metallization with lines formed by subtractive patterning and vias formed by damascene processes. The method includes depositing a dielectric layer over a conductive layer formed over a substrate, forming spacers surrounding mandrel sections formed over the dielectric layer, selectively depositing gap fill material adjacent the spacers, selectively removing the spacers, etching the dielectric layer and the conductive layer to expose a top surface of the substrate, depositing and planarizing an inter-layer dielectric, selectively forming openings in the dielectric layer, and filling the openings with a conductive material to define metal vias.

Abstract: A dual damascene interconnect structure with a fully aligned via integration scheme is formed with a partially removed etch stop layer. Portions of the etch stop layer are removed prior to dual damascene patterning of an interlevel dielectric layer formed above metal lines and after such patterning. Segments of the etch stop layer remain only around the vias, allowing the overall capacitance of the structure to be reduced.

Abstract: A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.

Abstract: A method for manufacturing a vertical transistor device includes forming a plurality of fins on a substrate, and forming a gate dielectric layer on the fins and on the substrate adjacent the fins. In the method, one or more sacrificial layers are formed on the gate dielectric layer, and portions of the gate dielectric layer and the one or more sacrificial layers are removed to define a plurality of gate regions. The method also includes depositing a dielectric fill layer in gaps left by the removed gate dielectric and sacrificial layers, and selectively removing the remaining portions of the one or more sacrificial layers to form a plurality of vacant areas in the gate regions. First and second gate structures are respectively formed in first and second vacant areas of the plurality of vacant areas. The first and second gate structures are recessed to a uniform height.

Abstract: Interconnect structures and methods for forming the interconnect structures generally include a subtractive etching process to form a fully aligned top via and metal line interconnect structure. The interconnect structure includes a top via and a metal line formed of an alternative metal other than copper or tungsten. A conductive etch stop layer is intermediate the top via and the metal line. The top via is fully aligned to the metal line.

Abstract: Integrated chips and methods of forming the same include forming a conductive layer over a lower conductive line. The conductive layer is etched to form a via on the lower conductive line. A first insulating layer is formed around the via. The first insulating layer is etched back to a height below a height of the via. An upper conductive line is formed on the via, making contact with at least a top surface and a side surface of the via.

Abstract: A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, SD, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, GD. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer.

Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.

Abstract: Dual damascene interconnect structures with fully aligned via integration schemes are formed using different dielectric materials having different physical properties. A low-k dielectric material having good fill capabilities fills nanoscopic trenches in such structures. Another dielectric material forms the remainder of the dielectric portion of the interconnect layer and has good reliability properties, though not necessarily good trench filling capability. The nanoscopic trenches may be filled with a flowable polymer using flowable chemical vapor deposition. A further dielectric layer having good reliability properties is deposited over the metal lines and dual damascene patterned to form interconnect line and via patterns. The patterned dielectric layer is filled with interconnect metal, thereby forming interconnect lines and fully aligned via conductors. The via conductors are electrically connected to previously formed metal lines below.

Abstract: A method for fabricating a semiconductor device including an ion-sensitive field-effect transistor (ISFET) with enhanced sensitivity includes forming a sawtooth microwell within a base structure formed on a semiconductor chip corresponding to an ISFET, including using a sawtooth mask to etch through the base structure to expose the semiconductor chip, removing the sawtooth mask, and forming a sawtooth macrowell from the sawtooth microwell.

Abstract: A semiconductor device includes a first transistor including a first vertical fin arranged between first bottom source or drain (S/D) region and first top S/D region, and a first recessed gate stack arranged on a sidewall of the first vertical fin. A second transistor includes second vertical fin arranged between a second bottom S/D region and second top S/D region, and a second recessed gate stack arranged on a sidewall of the second vertical fin. A first spacer contacts the sidewall of the first vertical fin and on the first recessed gate stack or the second recessed gate stack. A second spacer contacts the first spacer of the first transistor or the second transistor. The second spacer is on a sidewall of the top S/D region of the first transistor or second transistor. The inner spacer and the outer spacer include different materials.

Abstract: A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.

Abstract: Integrated circuits include back end of line metallization levels. An upper metallization level is on a lower metallization level and includes at least one top via-line interconnect structure in an interlayer dielectric. The lower metallization level includes at least one top via-line interconnect structure in an interlayer dielectric, wherein the top via is raised relative to the interlayer dielectric in the lower metallization level. The line in the upper metallization level contacts a top surface and sidewall portions of the top via raised above the interlevel dielectric. Also described are methods for fabricating the same.

Abstract: Methods and structures for pitch multiplication include forming a plurality of mandrel lines and non-mandrel lines on a target layer, wherein the non-mandrel lines include a protective spacer material about a top sidewall portion and a first spacer material about a lower sidewall portion, wherein the protective spacer material has a different etch selectivity than the first spacer material. The plurality of mandrel lines and non-mandrel lines are transferred into the target layer.

Abstract: Interconnect structures and methods for forming the interconnect structures generally include forming a dielectric layer over a substrate. The dielectric layer includes a dielectric layer top surface. A metal line is formed in the dielectric layer. The metal line includes a sacrificial upper region and a lower region. The sacrificial upper region is formed separately from the lower region and the lower region includes a lower region top surface positioned below the dielectric layer top surface. The sacrificial upper region is removed, thereby exposing the lower region top surface and forming a trench defined by the lower region top surface and sidewalls of the dielectric layer. An interconnect structure is deposited such that at least a portion of the interconnect structure fills the trench, thereby defining a fully aligned top via.

Abstract: A method of forming a semiconductor structure includes forming a first portion of a source/drain contact over a source/drain region of a fin-type field-effect transistor (FinFET), the source/drain region being formed over a fin providing a channel region of the FinFET and being adjacent a gate spacer surrounding a gate region of the FinFET. The method also includes forming a first interlayer dielectric (ILD) layer over the first portion of the source/drain contact, the gate spacer and the gate region, and forming a second ILD layer over the first ILD layer. The method further includes forming a second portion of the source/drain contact over the first portion of the source/drain contact in a first opening in the first ILD layer, and forming a third portion of the source/drain contact over the second portion of the source/drain contact in a second opening in the second ILD layer. The second opening is larger than the first opening.

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect in a first dielectric layer, and forming a second dielectric layer on the first dielectric layer. In the method, an etch stop layer is formed on the second dielectric layer, and a third dielectric layer is formed on the etch stop layer. The method also includes forming a trench in the third dielectric layer, wherein a bottom surface of the trench includes the etch stop layer. A second interconnect is formed in the trench on the etch stop layer, and a via is formed in the second dielectric layer. The via connects the second interconnect to the first interconnect.

Abstract: A device and a method to produce an augmented-laser (ATLAS) comprising a bi-stable resistive system (BRS) integrated in series with a semiconductor laser. The laser exhibits reduction/inhibition of the Spontaneous Emission (SE) below lasing threshold by leveraging the abrupt resistance switch of the BRS. The laser system comprises a semiconductor laser and a BRS operating as a reversible switch. The BRS operates in a high resistive state in which a semiconductor laser is below a lasing threshold and emitting in a reduced spontaneous emission regime, and a low resistive state in which a semiconductor laser is above or equal to a lasing threshold and emitting in a stimulated emission regime. The BRS operating as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using insulator-to-metal transition (IMT) materials or is formed using threshold-switching selectors (TSS).

Abstract: Embodiments of the present invention disclose a method forming a via and a trench. By utilizing a first etching process, a first metal layer of a multi-layered device to form a via, wherein the multi-layered device comprises the first metal layer and a second metal layer, wherein the first metal layer is formed directly on top of the second metal layer, wherein the second metal layer acts as an etch stop for the first etching process, wherein the first etching process does not affect the second metal layer. By utilizing a second etching process, the second metal layer of the multi-layered device to form a trench, wherein first metal layer is not affected by the second etching process, wherein the first etching process and the second etching process are two different etching process.