Patents by Inventor Chantal Arena

Chantal Arena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8887650
    Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 18, 2014
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20140326309
    Abstract: The invention relates to a method for preventing an electrical shortage between at least two layers of a semiconductor layer stack attached by the surface of one of its layers to a substrate via a conductive adhesive by providing an isolating layer on the side walls of the stack or by removing excess material after attaching the stack to the substrate. The invention also relates to a thin substrate CPV cell and to a solar cell assembly.
    Type: Application
    Filed: November 12, 2012
    Publication date: November 6, 2014
    Inventors: Rainer Krause, Bruno Ghyselen, Chantal Arena
  • Publication number: 20140312463
    Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.
    Type: Application
    Filed: June 30, 2014
    Publication date: October 23, 2014
    Inventor: Chantal Arena
  • Publication number: 20140306320
    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.
    Type: Application
    Filed: June 25, 2014
    Publication date: October 16, 2014
    Inventor: Chantal Arena
  • Publication number: 20140264371
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Soitec
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen
  • Publication number: 20140264408
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Soitec
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen, Ding Ding, Li Huang
  • Publication number: 20140264265
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of fainting semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Soitec
    Inventors: Chantal Arena, Jean-Philippe Debray, Richard Scott Kern
  • Patent number: 8836081
    Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 16, 2014
    Assignee: Soitec
    Inventor: Chantal Arena
  • Publication number: 20140217553
    Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.
    Type: Application
    Filed: November 23, 2011
    Publication date: August 7, 2014
    Applicants: ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY, Soitec
    Inventors: Chantal Arena, Ronald Thomas Bertram, JR., Ed Lindow, Subhash Mahajan, Ilsu Han
  • Patent number: 8765508
    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8741385
    Abstract: The present invention relates to the field of semiconductor processing and provides methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the method provides heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention provides radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: June 3, 2014
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, Jr., Ed Lindow
  • Patent number: 8692260
    Abstract: A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer formed on a support substrate, and a seed layer formed on the intermediate layer. An active device layer is grown or attached to the seed layer, or to a light confinement layer on the seed layer. The intermediate layer may be formed directly on the support layer, or may be formed by thinning an attached wafer of the intermediate material, which is then thinned to a desired thickness.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: April 8, 2014
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan J. Werkhoven
  • Publication number: 20140041584
    Abstract: Systems for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment is optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material.
    Type: Application
    Filed: October 16, 2013
    Publication date: February 13, 2014
    Applicant: Soitec
    Inventors: Chantal ARENA, Christiaan WERKHOVEN
  • Patent number: 8642995
    Abstract: Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 4, 2014
    Assignee: Soitec
    Inventor: Chantal Arena
  • Publication number: 20130327266
    Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 12, 2013
    Applicant: Soitec
    Inventors: Chantal ARENA, Christiaan WERKHOVEN
  • Patent number: 8598019
    Abstract: Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: December 3, 2013
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8585820
    Abstract: Methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment and methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: November 19, 2013
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Patent number: 8574968
    Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: November 5, 2013
    Assignees: Soitec, Arizona Board of Regents for and on Behalf of Arizona State University
    Inventors: Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, Jr., Ed Lindow, Subhash Mahajan, Ranjan Datta, Rahul Ajay Trivedi, Ilsu Han
  • Publication number: 20130285015
    Abstract: Radiation-emitting semiconductor devices include a first base region comprising an n-type III-V semiconductor material, a second base region comprising a p-type III-V semiconductor material, and a multi-quantum well structure disposed between the first base region and the second base region. The multi-quantum well structure includes at least three quantum well regions and at least two barrier regions. An electron hole energy barrier between a third of the quantum well regions and a second of the quantum well regions is less than an electron hole energy barrier between the second of the quantum well regions and a first of the quantum well regions. Methods of forming such devices include sequentially epitaxially depositing layers of such a multi-quantum well structure, and selecting a composition and configuration of the layers such that the electron hole energy barriers vary across the multi-quantum well structure.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventor: Chantal Arena
  • Patent number: 8545628
    Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 1, 2013
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven