Patents by Inventor Chantal Arena

Chantal Arena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090223442
    Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.
    Type: Application
    Filed: November 15, 2007
    Publication date: September 10, 2009
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20090223441
    Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods and equipment are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the precursor is provided at a mass flow of at least 50 g Group III element/hour for a time of at least 48 hours to facilitate high volume manufacture of the semiconductor material. Advantageously, the mass flow of the gaseous Group III precursor is controlled to deliver the desired amount.
    Type: Application
    Filed: November 15, 2007
    Publication date: September 10, 2009
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20090214785
    Abstract: The present invention relates to the field of semiconductor processing and provides apparatus and methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the invention comprises heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention comprises radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.
    Type: Application
    Filed: October 30, 2008
    Publication date: August 27, 2009
    Inventors: Chantal Arena, Christiaan J. Werkhoven, Ronald Thomas Bertram, JR., Ed Lindow
  • Publication number: 20090205563
    Abstract: The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.
    Type: Application
    Filed: November 16, 2007
    Publication date: August 20, 2009
    Applicant: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20090189185
    Abstract: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 10 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface.
    Type: Application
    Filed: April 6, 2009
    Publication date: July 30, 2009
    Applicant: ASM AMERICA, INC.
    Inventors: Chantal ARENA, Pierre TOMASINI, Nyles CODY, Matthias BAUER
  • Publication number: 20090178611
    Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.
    Type: Application
    Filed: November 15, 2007
    Publication date: July 16, 2009
    Applicant: S.O.I. TEC Silicon on Insulator Technologies S.A.
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20090098343
    Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.
    Type: Application
    Filed: July 25, 2008
    Publication date: April 16, 2009
    Inventors: Chantal ARENA, Christiaan J. Werkhoven, Ronald Thomas Bertram, JR., Ed Lidow, Subhash Mahajan, Ranjan Datta, Rahul Ajay Trivedi, Ilsu Han
  • Publication number: 20090091002
    Abstract: This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.
    Type: Application
    Filed: July 25, 2008
    Publication date: April 9, 2009
    Inventors: Chantal ARENA, Subhash Mahajan, Ranjan Datta
  • Patent number: 7514372
    Abstract: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 107 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: April 7, 2009
    Assignee: ASM America, Inc.
    Inventors: Chantal Arena, Pierre Tomasini, Nyles Cody, Matthias Bauer
  • Publication number: 20080303118
    Abstract: A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 11, 2008
    Inventors: Chantal Arena, Fabrice Letertre
  • Patent number: 7452757
    Abstract: Silicon-on-insulator (SOI) structures are provided by forming a single-crystal insulator over a substrate, followed by heteroepitaxy of a semiconductor layer thereover. Atomic layer deposition (ALD) is preferably used to form an amorphous insulator, followed by solid phase epitaxy to convert the layer into a single-crystal structure. Advantageously, the crystalline insulator has a lattice structure and lattice constant closely matching that of the semiconductor formed over it, and a ternary insulating material facilitates matching properties of the layers. Strained silicon can be formed without need for a buffer layer. An amorphous SiO2 layer can optionally be grown underneath the insulator. In addition, a buffer layer can be grown, either between the substrate and the insulator or between the insulator and the semiconductor layer, to produce desired strain in the active semiconductor layer.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: November 18, 2008
    Assignee: ASM America, Inc.
    Inventors: Christiaan J. Werkhoven, Ivo Raaijmakers, Chantal Arena
  • Patent number: 7427556
    Abstract: A method for blanket depositing a SiGe film comprises intermixing a silicon source, a germanium source and an etchant to form a gaseous precursor mixture. The method further comprises flowing the gaseous precursor mixture over a substrate under chemical vapor deposition conditions to deposit a blanket layer of epitaxial SiGe onto the substrate, whether patterned or un-patterned.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: September 23, 2008
    Assignee: ASM America, Inc.
    Inventors: Pierre Tomasini, Nyles Cody, Chantal Arena
  • Publication number: 20080026149
    Abstract: Chloropolysilanes are utilized in methods and systems for selectively depositing thin films useful for the fabrication of various devices such as microelectronic and/or microelectromechanical systems (MEMS).
    Type: Application
    Filed: May 24, 2007
    Publication date: January 31, 2008
    Applicant: ASM America, Inc.
    Inventors: Pierre Tomasini, Chantal Arena, Matthias Bauer, Nyles Cody, Ronald Bertram, Jianqing Wen, Matthew Stephens
  • Publication number: 20070293040
    Abstract: A method of filling a conductive material in a three dimensional integration feature formed on a surface of a wafer is disclosed. The feature is optionally lined with dielectric and/or adhesion/barrier layers and then filled with a liquid mixture containing conductive precursor, such as a solution with dissolved ruthenium precursor or a dispersion or suspension with conductive particles (e.g., gold, silver, copper), and the substrate is rotated while the mixture is on its surface. Then, the liquid carrier is dried from the feature, leaving a conductive layer in the feature. These two steps are optionally repeated until the feature is filled up with the conductor. Then, the conductor is annealed in the feature, thereby forming a dense conductive plug in the feature.
    Type: Application
    Filed: April 30, 2007
    Publication date: December 20, 2007
    Applicant: ASM NUTOOL, INC.
    Inventors: Ismail Emesh, Chantal Arena, Bulent Basol
  • Publication number: 20070264801
    Abstract: Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
    Type: Application
    Filed: May 9, 2006
    Publication date: November 15, 2007
    Inventors: Nyles Cody, Chantal Arena, Pierre Tomasini, Carlos Mazure
  • Publication number: 20070224786
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Application
    Filed: May 30, 2007
    Publication date: September 27, 2007
    Applicant: ASM AMERICA, INC.
    Inventors: Paul Brabant, Joseph Italiano, Chantal Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Publication number: 20060281322
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Application
    Filed: August 18, 2006
    Publication date: December 14, 2006
    Inventors: Paul Brabant, Joseph Italiano, Chantal Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
  • Publication number: 20060275546
    Abstract: An apparatus and method for processing a substrate is provided. The apparatus comprises a reaction chamber, a substrate holder within the chamber, and first and second injector components. The reaction chamber has an upstream end and a downstream end, between which the substrate holder is positioned. The substrate holder is configured to support a substrate so that the substrate is within a plane extending generally toward the upstream and downstream ends. The first injector component is at the upstream end of the chamber and is configured to inject a first thin gas curtain toward a substrate supported by the substrate holder. The first injector component is configured to inject the first curtain generally along a first plane that is parallel to a first side of the substrate. The second injector component is configured to inject a second thin gas curtain toward the first side of the substrate.
    Type: Application
    Filed: June 2, 2005
    Publication date: December 7, 2006
    Inventors: Chantal Arena, Chris Werkhoven, Ron Bertram
  • Publication number: 20060234504
    Abstract: Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.
    Type: Application
    Filed: January 30, 2006
    Publication date: October 19, 2006
    Inventors: Matthias Bauer, Chantal Arena, Ronald Bertram, Pierre Tomasini, Nyles Cody, Paul Brabant, Joseph Italiano, Paul Jacobson, Keith Weeks
  • Publication number: 20050092235
    Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 5, 2005
    Inventors: Paul Brabant, Joseph Italiano, Chantal Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer