Patents by Inventor Chantal Arena

Chantal Arena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8278193
    Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: October 2, 2012
    Assignee: SOITEC
    Inventor: Chantal Arena
  • Patent number: 8247314
    Abstract: Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: August 21, 2012
    Assignee: Soitec
    Inventor: Chantal Arena
  • Publication number: 20120199845
    Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer.
    Type: Application
    Filed: February 3, 2011
    Publication date: August 9, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Christiaan J. Werkhoven, Chantal Arena
  • Patent number: 8236593
    Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: August 7, 2012
    Assignees: Soitec, Arizona Board of Regents for and on Behalf of Arizona State University
    Inventors: Chantal Arena, Subhash Mahajan, Ilsu Han
  • Publication number: 20120187541
    Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
    Type: Application
    Filed: April 5, 2012
    Publication date: July 26, 2012
    Applicants: COMMISSARIAT A. L'ENERGIE ATOMIQUE, S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
    Inventors: Chantal Arena, Laurent Clavelier, Marc Rabarot
  • Patent number: 8197597
    Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: June 12, 2012
    Assignee: Soitec
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20120132922
    Abstract: A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction.
    Type: Application
    Filed: July 8, 2009
    Publication date: May 31, 2012
    Applicant: SOITEC
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Patent number: 8178427
    Abstract: The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: May 15, 2012
    Assignees: Commissariat a. l'Energie Atomique, S.O.I. Tec Silicon on Insulator Technologies, S.A.
    Inventors: Chantal Arena, Laurent Clavelier, Marc Rabarot
  • Publication number: 20120085400
    Abstract: Methods of fabricating photovoltaic devices include forming a plurality of subcells in a vertically stacked arrangement on the semiconductor material, each of the subcells being formed at a different temperature than an adjacent subcell such that the adjacent subcells have differing effective band-gaps. The methods of fabricating also include inverting the structure, attaching another substrate to the second semiconductor material, and removing the substrate. For example, each of the subcells may comprise a III-nitride material, and each subsequent subcell may include an indium content different than the adjacent subcell. Novel structures may be formed using such methods.
    Type: Application
    Filed: May 26, 2010
    Publication date: April 12, 2012
    Applicant: SOITEC
    Inventors: Chantal Arena, Heather McFelea
  • Patent number: 8154022
    Abstract: A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: April 10, 2012
    Assignee: Soitec
    Inventors: Chantal Arena, Fabrice Letertre
  • Publication number: 20120048182
    Abstract: The invention relates to a method and system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The method includes reacting an amount of a gaseous Group III precursor having one or more gaseous gallium precursors as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber; and supplying sufficient energy to the gaseous gallium precursor(s) prior to their reacting so that substantially all such precursors are in their monomer forms. The system includes sources of the reactants, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their component monomers.
    Type: Application
    Filed: November 3, 2011
    Publication date: March 1, 2012
    Inventors: Chantal Arena, Christiaan Werkhoven
  • Publication number: 20110305835
    Abstract: Systems and methods for the gas treatment of one or more substrates include at least two gas injectors in a reaction chamber, one of which may be movable. The systems may also include a substrate support structure for holding one or more substrates disposed within the reaction chamber. The movable gas injector may be disposed between the substrate support structure and another gas injector. The gas injectors may be configured to discharge different process gasses therefrom. The substrate support structure may be rotatable around an axis of rotation.
    Type: Application
    Filed: June 14, 2010
    Publication date: December 15, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Ronald Thomas Bertram, JR., Chantal Arena, Ed Lindow
  • Publication number: 20110284863
    Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.
    Type: Application
    Filed: March 23, 2011
    Publication date: November 24, 2011
    Applicants: Arizona Board of Regents for and on Behalf of Arizona State University, S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Ed Lindow, Chantal Arena, Ronald Bertram, Ranjan Datta, Subhash Mahajan
  • Publication number: 20110277681
    Abstract: The present invention provides improved gas injectors for use with chemical vapour deposition (CVD) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high volume manufacturing of GaN substrates.
    Type: Application
    Filed: February 17, 2010
    Publication date: November 17, 2011
    Inventors: Chantal Arena, Ronald Thomas Bertram, JR., Ed Lindow
  • Publication number: 20110212546
    Abstract: A semiconductor growth system includes a chamber and a source of electromagnetic radiation. A detector is arranged to detect absorption of radiation from the source by a chloride- based chemical of the reaction chamber. A control system controls the operation of the chamber in response to the absorption of radiation by the chloride-based chemical. The control system controls the operation of the chamber by adjusting a parameter of the reaction chamber.
    Type: Application
    Filed: July 21, 2009
    Publication date: September 1, 2011
    Inventors: Ronald Thomas Bertram Jr., Chantal Arena, Christiaan J. Werkhoven, Michael Albert Tischler, Vasil Vorsa, Andrew D. Johnson
  • Publication number: 20110212603
    Abstract: Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods.
    Type: Application
    Filed: May 12, 2011
    Publication date: September 1, 2011
    Inventors: Chantal Arena, Ilsu Han
  • Publication number: 20110156212
    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.
    Type: Application
    Filed: July 23, 2009
    Publication date: June 30, 2011
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventor: Chantal Arena
  • Publication number: 20110101373
    Abstract: A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer (110) formed on a support substrate (102), and a seed layer (120) formed on the intermediate layer. An active device layer (124) is grown or attached to the seed layer, or to a light confinement layer on the seed layer. The intermediate layer may be formed directly on the support layer, or may be formed by thinning an attached wafer of the intermediate material, which is then thinned to a desired thickness.
    Type: Application
    Filed: September 21, 2009
    Publication date: May 5, 2011
    Applicant: S.O.I.TEC Silicon on Insulator Technologies
    Inventors: Chantal Arena, Christiaan J. Werkhoven
  • Publication number: 20110057294
    Abstract: A method of fabricating a device layer structure includes providing a III-nitride semiconductor layer which is bonded to a bonding substrate. A device layer structure is formed on a nitrogen polar surface of the III-nitride semiconductor layer. The device layer structure includes an indium gallium nitride layer with a metal polar surface adjacent to the nitrogen polar surface of the III-nitride semiconductor layer.
    Type: Application
    Filed: May 22, 2009
    Publication date: March 10, 2011
    Inventor: Chantal Arena
  • Patent number: 7902045
    Abstract: A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: March 8, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Chantal Arena, Fabrice Letertre