Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.

Abstract: A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.

Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.

Abstract: A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

Abstract: A method comprises removing a portion of a fin to form a trench over a lower portion of the fin, wherein the lower portion is formed of a first semiconductor material, growing a second semiconductor material in the trench to form a middle portion of the fin, forming a first carbon doped layer over the middle portion of the fin, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin, replacing outer portions of the upper portion of the fin with a second carbon doped layer and drain/source regions, wherein the first carbon doped layer and the second carbon doped layer are separated by the upper portion of the fin and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.

Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.

Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.

Abstract: A back side illumination (BSI) image sensor with stacked grid shifting is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid segment is arranged over the pixel sensor and has a metallic grid opening therein. A center of the metallic grid opening is laterally shifted from a center of the pixel sensor. A dielectric grid segment is arranged over the metallic grid and has a dielectric grid opening therein. A center of the dielectric grid opening is laterally shifted from the center of the pixel sensor. A method for manufacturing the BSI image sensor is also provided.

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function.

Abstract: A method of forming low-k interconnect structure is disclosed, which comprises: providing at least one protruding structure on a substrate traversing between a first connection region to a second connection region defined thereon; performing anodic oxidation on the substrate having the protruding structure; forming one or more nanowire interconnect in the protruding structure traversing between the first connection region and the second connection region; the nanowire interconnect being surrounded by a dielectric layer formed during the anodic oxidation.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

Abstract: A method comprises recessing a substrate to form a fin enclosed by an isolation region, wherein the substrate is formed of a first semiconductor material, recessing the fin to form a trench over a lower portion of the fin, growing a second semiconductor material in the trench to form a middle portion of the fin through a first epitaxial process, forming a first carbon doped layer over the lower portion through a second epitaxial process, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin through a third epitaxial process, forming a first source/drain region through a fourth epitaxial process, wherein a second carbon doped layer is formed underlying the first source/drain region and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.

Abstract: Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation.

Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: An embodiment is a structure including a first active device in a first region of a substrate, the first active device including a first layer of a two-dimensional (2-D) material, the first layer having a first thickness, and a second active device in a second region of the substrate, the second active device including a second layer of the 2-D material, the second layer having a second thickness, the 2-D material including a transition metal dichalcogenide (TMD), the second thickness being different than the first thickness.

Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.