Abstract: A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.

Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.

Abstract: A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor FinFET is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.

Abstract: The disclosure relates to a semiconductor device and methods of forming same. A representative structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate having a channel region disposed between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprise a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region.

Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

Abstract: Systems and methods are provided for annealing a semiconductor structure using microwave radiation. A semiconductor structure is provided. One or more energy-converting materials capable of increasing the semiconductor structure's absorption of microwave radiation are provided. Microwave radiation is applied to the energy-converting materials and the semiconductor structure to anneal the semiconductor structure for fabricating semiconductor devices. First local temperatures associated with one or more first zones of the semiconductor structure are detected. The microwave radiation applied to the energy-converting materials and the semiconductor structure is adjusted based at least in part on the detected first local temperatures.

Abstract: Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation.

Abstract: An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region.

Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.

Abstract: The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate comprising a channel region between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprising a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region.

Abstract: Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device layer. The device layer is arranged within an upper surface the device layer. A crack stop is formed, which surrounds the device structure and reinforces the semiconductor wafer to prevent cracking during dicing. A laser is used to form a groove along a scribe line outside the crack stop. The groove extends completely through the device layer, and into an upper surface region of the semiconductor wafer. The semiconductor wafer is then cut along the grooved scribe line with a cutting blade to singulate the semiconductor wafer into two or more die. By extending the groove completely through the device layer, the method avoids damage to the device layer caused by the blade saw, and thus avoids an associated performance degradation of the device structure.

Abstract: A representative method for fabricating a field effect transistor comprises forming a source region and a drain region disposed in a substrate; forming a gate structure over the substrate, the gate structure comprising sidewalls and a top surface, the gate structure interposing the source region and the drain region; forming a contact etch stop layer (CESL) over at least a portion of the top surface of the gate structure; forming an interlayer dielectric layer over the CESL; forming a gate contact extending through the interlayer dielectric layer; and forming a source contact and a drain contact extending through the interlayer dielectric layer, wherein a first distance between an edge of the source contact and a first corresponding edge of the CESL is about 1 nm to about 10 nm.

Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.

Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.

Abstract: An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region.

Abstract: Systems and methods are provided for annealing a semiconductor structure using microwave radiation. A semiconductor structure is provided. One or more energy-converting materials capable of increasing the semiconductor structure's absorption of microwave radiation are provided. Microwave radiation is applied to the energy-converting materials and the semiconductor structure to anneal the semiconductor structure for fabricating semiconductor devices. First local temperatures associated with one or more first zones of the semiconductor structure are detected. The microwave radiation applied to the energy-converting materials and the semiconductor structure is adjusted based at least in part on the detected first local temperatures.

Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact.