Abstract: Provided are a memory device and a method of forming the same. The memory device includes a plurality of bit lines extending along a first direction; a plurality of word lines extending along a second direction different from the first direction; a plurality of memory pillars; and a selector. The plurality of word lines are disposed over the plurality of bit lines. The plurality of memory pillars are disposed between the plurality of bit lines and the plurality of word lines, and respectively positioned at a plurality of intersections of the plurality of bit lines and the plurality of word lines. The selector is disposed between the plurality of memory pillar and the plurality of word lines. The selector extends from a top surface of one memory pillar to cover a top surface of an adjacent memory pillar. A semiconductor device having the memory device is also provided.

Abstract: A panel assembly (100) of a ceiling-embedded air conditioner and a ceiling-embedded air conditioner having the same are provided. The panel assembly has a reference axis, the panel frame (2) is provided with an adjustable port (231), the adjustable port has a port inner edge (2311) and a port outer edge (2312) close to and away from the reference axis; a projection of the port inner edge is located on a side of the projection of the port outer edge facing an outer end; the panel assembly comprises an adjustable plate (3) arranged at the adjustable port, and the adjustable plate has a plate inner edge (33) and a plate outer edge (34) close to and away from the reference axis; in the low-wind-feeling position, the plate inner edge is close to or linked to the port inner edge, and a radial air outlet is formed between the plate outer edge and the port outer edge to output air in a direction away from the reference axis.

Abstract: A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.

Abstract: A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.

Abstract: Disclosed are the preparing method of a pentacyclic triterpenoid saponin compound and a drug composition, and in particular the method of the pentacyclic triterpenoid saponin compounds as shown in formulae (I) to (XVI) in the preparation of a drug for preventing or treating a disease mediated by AMPK and/or ERR?, comprising the preparation of a drug for preventing or treating diseases such as a liver disease, respiratory system disease, metabolic disease, autoimmune disease, cardiovascular and cerebrovascular disease, kidney disease, central nervous system disease or muscular dystrophy. The definition of formulae (I) to (XVI) is the same as the definition in the specification.

Abstract: A panel assembly includes a panel, a panel frame, and an air guide plate. The panel frame is in annular shape and fitted over the panel. The panel frame includes a plurality of air outlets spaced apart from each other and surrounding the panel, and an air baffle rib provided at an appearance surface of the panel frame and located on a side of the air outlets away from the panel. The air guide plate is movably arranged at the air outlets.

Abstract: A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.

Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.

Abstract: A semiconductor package disposed on a base is provided. The semiconductor package includes a semiconductor chip and a redistribution layer (RDL) structure. The semiconductor chip includes a first chip pad and a second chip pad. The redistribution layer (RDL) structure partially covers the semiconductor chip and is separated from the base by the semiconductor chip. The RDL structure includes a redistribution layer (RDL) trace having a first terminal and a second terminal. The first terminal of the RDL trace is electrically coupled to the first chip pad. The second terminal of the RDL trace is electrically coupled to the second chip pad.

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.

Abstract: Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Abstract: A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.

Abstract: This application discloses a method and an apparatus for modifying a file name and a storage medium. The method includes: displaying a first target file of which a name is to be modified, the first target file being currently located under a target level directory, and a current file name of the first target file being a first file name; receiving a file name modification operation for the first target file, the file name modification operation being used for instructing to perform a name modification operation on object files in a file set, and the object files being located under the target level directory and having a same file name as the first target file; and modifying file names of the object files in the file set from the first file name to a second file name in response to the file name modification operation.

Abstract: Embodiments of the present disclosure provide a method for file backup, an electronic device and a computer program product. The method comprises: dividing a set of files to be backed up into a plurality of subsets of files, files in each of the plurality of subsets of files being of a same file type. The method also comprises: generating a plurality of backup files based on the plurality of subsets of files respectively, the plurality of backup files corresponding to a plurality of file types of files in the plurality of subsets of files respectively. The method further comprises: generating an overall backup file corresponding to the set of files based on the plurality of backup files.

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Abstract: A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.

Abstract: This document describes techniques and apparatuses for supporting web components associated with a document object model (DOM) corresponding to a data file in a web testing environment. A user interaction, relative to a web page or web application from which the DOM is rendered, is monitored in the web testing environment. The monitoring identifies a target element selected by the user that is referenced in a shadow DOM associated with the DOM. One or more parent shadow host elements of the DOM are identified relative to the target element. The one or more shadow host elements define a reduced path, with respect to a tree data structure representing the DOM and the shadow DOM, for linking a document object of the DOM to the target element. Indicia identifying the one or more shadow host elements as linking the document object of the DOM to the target element are recorded.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. The storage element layer has a first inclined sidewall, the top electrode has a second inclined sidewall, and an angle of the first inclined sidewall is greater than an angle of the second inclined sidewall. A semiconductor device having the memory cell is also provided.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer.