Abstract: Embodiments of this application provide a page processing method and related apparatus. The method includes previewing a target page in an application program; obtaining a page structure of the previewed target page, the page structure of the target page identifying a layout of page elements of the target page in the target page; obtaining a page structure of a skeleton screen corresponding to the target page based on the page structure of the target page, the page structure of the skeleton screen identifying a layout of placeholder elements of the skeleton screen on the skeleton screen, the placeholder elements being obtained by processing the page elements; and generating a view file of the skeleton screen according to the page structure of the skeleton screen, the skeleton screen being displayed before the target page is loaded.

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

Abstract: An electronic device receives an interface calling request for a target interface in an application program. The interface calling request includes interface calling information of the target interface. The device performs an interface query in a simulated interface set that simulates real interfaces in the application program. In accordance with a determination, based on the interface query, that a target simulation interface corresponding to the target interface exists in the simulated interface set, the device intercepts the interface calling request. The device compares the intercepted interface calling information with interface configuration information of the target simulated interface. In accordance with a determination that the interface calling information matches the interface configuration information, the device obtains simulated response data corresponding to the target simulation interface. The device outputs calling response data of the interface calling request.

Abstract: A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.

Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer.

Abstract: A phase change memory device includes a bottom conductive line, a dielectric layer, a bottom memory layer, and a top electrode. The dielectric layer covers the bottom conductive line. The bottom memory layer is in the dielectric layer and is electrically connected to the bottom conductive line. The bottom memory layer includes a tapered portion and a neck portion. The tapered portion is over the bottom conductive line and is tapered toward the bottom conductive line. The neck portion is directly between the tapered portion and the bottom conductive line. The neck portion has a substantially constant width. The top electrode is over and electrically connected to the bottom memory layer.

Abstract: A serial data processing device includes an offset detector circuit and an offset calibration circuit. The offset detector circuit is configured to store a plurality of tokens, and to receive a first data signal from a host device, and to detect an offset in the received first data signal according to the plurality of tokens, in order to generate a calibration signal, in which each of the tokens includes at least one predetermined logic value, and numbers of the at least one predetermined logic value in each of the plurality of tokens are different. The offset calibration circuit is configured to calibrate the received first data signal according to the calibration signal, in order to generate a second data signal.

Abstract: The present disclosure relates to an antibody against Aquaporin-4 (AQP4). These peptide-specific AQP4 antibodies play a role to create a NMO model and contribute for investigating the NMO disease mechanisms and developing the strategy of the treatment.

Abstract: A method of forming a phase change random access memory (PCRAM) device includes forming a phase change element over a bottom electrode and a top electrode over the phase change element, forming a protection layer around the phase change element, and forming a nitrogen-containing sidewall spacer layer around the protection layer after forming the protection layer.

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, a storage element layer, and a protective layer. The storage element layer is disposed between the bottom and top electrodes. The protective layer covers the storage element layer and the top electrode, and a material of the protective layer is derived from the storage element layer. A semiconductor device having the memory cell is also provided.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.

Abstract: A method for estimating a signal-to-noise ratio of a received digital radio signal. The estimating method includes a detecting step consisting in recovering a received synchronization symbol contained in the received digital radio signal, and an estimating step configured to determine the signal-to-noise ratio of the received digital radio signal, depending on the difference between a first received synchronization signal and a second received synchronization signal. The first and second received synchronization signals are comprised in the received synchronization symbol.

Abstract: The present disclosure relates to a heat radiator and a turbo fracturing unit comprising the same. The heat radiator includes: a cabin; a heat radiation core disposed at the inlet and configured to allow a gas to pass therethrough; a gas guide device disposed at the outlet and configured to suction the air within the cabin to the outlet; and noise reduction core disposed within the cabin, which is of a structure progressively converging to the outlet. The heat radiator is configured to enable the gas to enter the cabin via the inlet, then sequentially pass through the heat radiation core, a surface of the noise reduction core and the gas guide device, and finally be discharged out of the cabin. The heat radiator according to the present disclosure is a suction-type heat radiator which can regulate the speed of the gas guide device based on the temperature of the gas at the inlet, thereby avoiding energy waste and unnecessary noise.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer.

Abstract: A light emitting apparatus includes a housing, a connector, a light source, a control module board, and an antenna. The housing includes an inner space. The light source is located in the inner space. The control module board is located in the connector, wherein an accommodation space is formed by the housing and the control module board. The antenna is located in the accommodation space.

Abstract: This application relates to a message processing method and apparatus, a storage medium, and a computer device. The method includes: receiving a session message associated with an interactive session of a social application; while rendering the session message in a session interface corresponding to the interactive session of the social application: identifying a child application identifier in the session message; invoking plug-in code corresponding to the child application identifier in the social application; obtaining, from the social application, shared data corresponding to the child application identifier using the plug-in code; and dynamically presenting the shared data in the session message.