Patents by Inventor Chao Wen

Chao Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND APPARATUS FOR DEALING WITH NEGOTIATION PROCEDURE INITIATED BY REQUEST ACTION FRAME THROUGH RESPONDING WITH ACKNOWLEDGEMENT CONTROL FRAME OR TIME-CONSTRAINED RESPONSE ACTION FRAME
    Publication number: 20230188266
    Abstract: One wireless communication method includes: receiving a request action frame; and in response to the request action frame, generating and sending an acknowledgement (ACK) control frame that is configured to serve as a response action frame for the request action frame, wherein the response action frame is not solicited by the request action frame. Another wireless communication method includes: receiving a request action frame; and in response to the request action frame, generating and sending an acknowledgement (ACK) control frame and a time-constrained response action frame following the ACK control frame, wherein the time-constrained response action frame is solicited by the request action frame.
    Type: Application
    Filed: November 24, 2022
    Publication date: June 15, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chien-Fang Hsu, Cheng-Ying Wu, Chao-Wen Chou, Yongho Seok
  • Method for manufacturing a semiconductor device having an interconnect structure over a substrate
    Patent number: 11658069
    Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih
  • Package structure
    Patent number: 11658392
    Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • Reallocation of power between electronic components
    Patent number: 11644881
    Abstract: Techniques for reallocating power between a plurality of electronic components and a connection port of a computing system are described. In operation, operational state of an electronic component from amongst multiple electronic components is analysed. Based on the operational state of the electronic component, an unused power available with the electronic components is determined. Based on the availability of the unused power, a default power level associated with the connection port is increased, where the default power level is a predefined power allocated to the connection port for operation.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 9, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chao Wen Cheng, Po Ying Chih, Yen Tang Chang
  • VERIFICATION METHOD AND VERIFICATION SYSTEM FOR INFORMATION AND COMMUNICATION SAFETY PROTECTION MECHANISM
    Publication number: 20230137661
    Abstract: A verification method and a verification system for an information and communication safety protection mechanism are provided. The verification methods includes: selecting a target malicious program, and collecting at least one behavioral trace of the target malicious program; providing a target machine and deploying a protection mechanism to be tested for the target machine; configuring the target machine to reproduce the at least one behavioral trace; and determining whether the protection mechanism to be tested detects an abnormal event, so as to verify an effectiveness of the protection mechanism to be tested.
    Type: Application
    Filed: November 25, 2021
    Publication date: May 4, 2023
    Inventors: CHAO-WEN LI, CHING-HAO MAO, WEN-YA LIN, WEN-HSI TU
  • SEMICONDCUTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230123652
    Abstract: A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Inventor: Chao-Wen LAY
  • Configuring power level of central processing units at boot time
    Patent number: 11630500
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, an unloaded component is detected. The unloaded component remains undetected upon completion of a boot process of the computing device. Thereafter, a power budget allocated to the unloaded component is determined. The power budget may be based on the thermal design power (TDP) of the computing device. Based on the power budget, a power configuration of the CPU is changed from a default power level to a high-performance power level, wherein the default power level corresponds to the TDP of the computing device and the high-performance power level is a power level above the default power level and upto a maximum power level of the CPU.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 18, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Yen Tang Chang, Chao Wen Cheng, Chien Chen Su, Po Ying Chih
  • PACKAGE HAVING MULTIPLE CHIPS INTEGRATED THEREIN AND MANUFACTURING METHOD THEREOF
    Publication number: 20230116818
    Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • MICRO-LIGHT-EMITTING DIODE DISPLAY PANEL
    Publication number: 20230104979
    Abstract: A micro-light-emitting diode (microLED) display panel includes a substrate; a plurality of microLEDs disposed and arranged in rows and columns on the substrate; a driver disposed on the substrate; a plurality of first blocking walls respectively disposed between rows of the microLEDs; and a plurality of second blocking walls respectively disposed between the microLEDs of the same row.
    Type: Application
    Filed: February 23, 2022
    Publication date: April 6, 2023
    Inventors: Biing-Seng Wu, Chao-Wen Wu, Hsing-Ying Lee, Chun-Bin Wen
  • Medical device with control circuitry to improve communication quality
    Patent number: 11622325
    Abstract: A method for managing power during communication with an implantable medical device, including establishing a communications link, utilizing a power corresponding to a session start power, to initiate a current session between an implantable medical device (IMD) and external device. A telemetry break condition of the communications link is monitored during the current session. The power utilized by the IMD is adjusted between low and high power levels, during the current session based on the telemetry break condition. The number of sessions is counted, including the current session and one or more prior sessions, in which the IMD utilized the higher power level, and a level for the session start power to be utilized to initiate a next session following the current session is adaptively learned based on the counting of the number of sessions.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 4, 2023
    Assignee: Pacesetter, Inc.
    Inventors: Perry Li, Lequan Zhang, Xing Pei, Jeffery Crook, Yongjian Wu, Jun Yang, Chao-Wen Young
  • METHOD AND STRUCTURE FOR A BRIDGE INTERCONNECT
    Publication number: 20230095134
    Abstract: Embodiments utilize a bridge die that directly bonds to and bridges two or more device dies. Each of the device dies can have additional device dies stacked thereupon. In some embodiments, the bridge die can bridge device dies disposed both under and over the bridge die. In some embodiments, several bridge dies may be used to bridge a device die to other adjacent device dies.
    Type: Application
    Filed: March 18, 2022
    Publication date: March 30, 2023
    Inventors: Ming-Fa Chen, Min-Chien Hsiao, Chih-Chia Hu, Han-Ping Pu, Ching-Yu Huang, Chen-Sheng Lin, Sung-Feng Yeh, Chao-Wen Shih
  • Integrated Circuit Packages
    Publication number: 20230067035
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 2, 2023
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Package and method of fabricating the same
    Patent number: 11587894
    Abstract: Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Tzuan-Horng Liu, Jen-Li Hu
  • BOTTOM-EMISSION LIGHT-EMITTING DIODE DISPLAY
    Publication number: 20230045824
    Abstract: A bottom-emission light-emitting diode (LED) display includes a transparent substrate, a plurality of LEDs bonded on the substrate, a packaging layer formed on the substrate to cover the LEDs, and a reflecting layer formed on the packaging layer to reflect light emitted by the plurality of LEDs. The reflecting layer has a non-smooth shape or the packaging layer has different refractivities.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Inventors: Biing-Seng Wu, Chao-Wen Wu, Chun-Bin Wen, Chien-Lin Lai, Hsing-Ying Lee
  • IMPLANTABLE MEDICAL DEVICE AND METHOD FOR MANAGING ADVERTISING AND SCANNING SCHEDULES
    Publication number: 20230039943
    Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.
    Type: Application
    Filed: October 25, 2022
    Publication date: February 9, 2023
    Inventors: Yongjian Wu, Jyoti Bhayana, Chao-Wen Young, Tejpal Singh, Samir Shah
  • POWER SUPPLIES
    Publication number: 20230028599
    Abstract: Structures and functions of power supplies are disclosed. In an example, a power supply includes a power factor correction circuit and a bypass circuit. The bypass circuit bypasses the power factor correction circuit when the switch of the bypass circuit is on in response to a predetermined range of input power of the power supply. The bypass circuit also includes a delay circuit to delay the activation of the bypass circuits in response to the predetermined range of input power of the power supply for a predetermined time period.
    Type: Application
    Filed: December 20, 2019
    Publication date: January 26, 2023
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Chao-Wen Cheng
  • CARD RETAINERS
    Publication number: 20230028263
    Abstract: In an example, a card retainer may include a latch to removably engage with a free end of an expansion card. Further, a card retainer may include a pivot mount to attach the latch to a system board of a computing device. In some examples, the latch is movable about the pivot mount between an open position and a closed position. The latch may exert a bias force on the free end of the expansion card in order to retain the expansion card to the system board in a secure manner when the latch is disposed in the closed position.
    Type: Application
    Filed: January 10, 2020
    Publication date: January 26, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Xiang Ma, Chan Woo Park, Baosheng Zhang, Richard Lin, Fangyong Dai, Chao-Wen Cheng, Chien Fa Huang, Roger Allen Pearson
  • Package having multiple chips integrated therein and manufacturing method thereof
    Patent number: 11562983
    Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Top emission microLED display and bottom emission microLED display and a method of forming the same
    Patent number: 11552127
    Abstract: A microLED display includes a first main substrate, microLEDs disposed above the first main substrate, a first light blocking layer disposed above the first main substrate to define emission areas, a light guiding layer disposed in the emission areas, and a plurality of connecting structures disposed in the emission areas respectively and electrically connected with the microLEDs.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: January 10, 2023
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chao-Wen Wu
  • Package structures and methods of fabricating the same
    Patent number: 11552074
    Abstract: A package structure and a method of fabricating the same are provided. The method includes bonding a first die and a second die to a wafer in a first die region of the wafer hybrid bonding; bonding a first dummy structure to the wafer in the first die region and a first scribe line of the wafer; and singulating the wafer and the first dummy structure along the first scribe line to form a stacked integrated circuit (IC) structure.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih