Patents by Inventor Chao Wen

Chao Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230104979
    Abstract: A micro-light-emitting diode (microLED) display panel includes a substrate; a plurality of microLEDs disposed and arranged in rows and columns on the substrate; a driver disposed on the substrate; a plurality of first blocking walls respectively disposed between rows of the microLEDs; and a plurality of second blocking walls respectively disposed between the microLEDs of the same row.
    Type: Application
    Filed: February 23, 2022
    Publication date: April 6, 2023
    Inventors: Biing-Seng Wu, Chao-Wen Wu, Hsing-Ying Lee, Chun-Bin Wen
  • Patent number: 11622325
    Abstract: A method for managing power during communication with an implantable medical device, including establishing a communications link, utilizing a power corresponding to a session start power, to initiate a current session between an implantable medical device (IMD) and external device. A telemetry break condition of the communications link is monitored during the current session. The power utilized by the IMD is adjusted between low and high power levels, during the current session based on the telemetry break condition. The number of sessions is counted, including the current session and one or more prior sessions, in which the IMD utilized the higher power level, and a level for the session start power to be utilized to initiate a next session following the current session is adaptively learned based on the counting of the number of sessions.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 4, 2023
    Assignee: Pacesetter, Inc.
    Inventors: Perry Li, Lequan Zhang, Xing Pei, Jeffery Crook, Yongjian Wu, Jun Yang, Chao-Wen Young
  • Publication number: 20230095134
    Abstract: Embodiments utilize a bridge die that directly bonds to and bridges two or more device dies. Each of the device dies can have additional device dies stacked thereupon. In some embodiments, the bridge die can bridge device dies disposed both under and over the bridge die. In some embodiments, several bridge dies may be used to bridge a device die to other adjacent device dies.
    Type: Application
    Filed: March 18, 2022
    Publication date: March 30, 2023
    Inventors: Ming-Fa Chen, Min-Chien Hsiao, Chih-Chia Hu, Han-Ping Pu, Ching-Yu Huang, Chen-Sheng Lin, Sung-Feng Yeh, Chao-Wen Shih
  • Publication number: 20230067035
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 2, 2023
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Patent number: 11587894
    Abstract: Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Tzuan-Horng Liu, Jen-Li Hu
  • Publication number: 20230045824
    Abstract: A bottom-emission light-emitting diode (LED) display includes a transparent substrate, a plurality of LEDs bonded on the substrate, a packaging layer formed on the substrate to cover the LEDs, and a reflecting layer formed on the packaging layer to reflect light emitted by the plurality of LEDs. The reflecting layer has a non-smooth shape or the packaging layer has different refractivities.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Inventors: Biing-Seng Wu, Chao-Wen Wu, Chun-Bin Wen, Chien-Lin Lai, Hsing-Ying Lee
  • Publication number: 20230039943
    Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.
    Type: Application
    Filed: October 25, 2022
    Publication date: February 9, 2023
    Inventors: Yongjian Wu, Jyoti Bhayana, Chao-Wen Young, Tejpal Singh, Samir Shah
  • Publication number: 20230028263
    Abstract: In an example, a card retainer may include a latch to removably engage with a free end of an expansion card. Further, a card retainer may include a pivot mount to attach the latch to a system board of a computing device. In some examples, the latch is movable about the pivot mount between an open position and a closed position. The latch may exert a bias force on the free end of the expansion card in order to retain the expansion card to the system board in a secure manner when the latch is disposed in the closed position.
    Type: Application
    Filed: January 10, 2020
    Publication date: January 26, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Xiang Ma, Chan Woo Park, Baosheng Zhang, Richard Lin, Fangyong Dai, Chao-Wen Cheng, Chien Fa Huang, Roger Allen Pearson
  • Publication number: 20230028599
    Abstract: Structures and functions of power supplies are disclosed. In an example, a power supply includes a power factor correction circuit and a bypass circuit. The bypass circuit bypasses the power factor correction circuit when the switch of the bypass circuit is on in response to a predetermined range of input power of the power supply. The bypass circuit also includes a delay circuit to delay the activation of the bypass circuits in response to the predetermined range of input power of the power supply for a predetermined time period.
    Type: Application
    Filed: December 20, 2019
    Publication date: January 26, 2023
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Chao-Wen Cheng
  • Patent number: 11562983
    Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11552074
    Abstract: A package structure and a method of fabricating the same are provided. The method includes bonding a first die and a second die to a wafer in a first die region of the wafer hybrid bonding; bonding a first dummy structure to the wafer in the first die region and a first scribe line of the wafer; and singulating the wafer and the first dummy structure along the first scribe line to form a stacked integrated circuit (IC) structure.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11552127
    Abstract: A microLED display includes a first main substrate, microLEDs disposed above the first main substrate, a first light blocking layer disposed above the first main substrate to define emission areas, a light guiding layer disposed in the emission areas, and a plurality of connecting structures disposed in the emission areas respectively and electrically connected with the microLEDs.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: January 10, 2023
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chao-Wen Wu
  • Patent number: 11543188
    Abstract: A temperature plate device includes a plate body and a bent structure. The plate body includes a first plate and a second plate. A chamber is defined by the first plate and the second plate. The first plate has a first step section. The second plate has a second step section corresponding to the first step section. The bent structure is connected to and traverses the first step section between the first step section and the second step section.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: January 3, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Kuang Tan, Shih-Kang Lin, Kuo-Ying Lee, Ting-Yuan Wu, Chao-Wen Lu
  • Patent number: 11537189
    Abstract: Example implementations relate to power supply controllers. In some examples, a controller can include instructions to: set a power threshold for a power supply coupled to a computing component when the computing component is operating in a first state, determine when the computing component is alternating from the first state to a second state, and allow the power supply to exceed the power threshold for a fixed period of time in response to the computing component alternating from the first state to the second state.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 27, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Roger A. Pearson, Jonathan D. Bassett
  • Publication number: 20220395953
    Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.
    Type: Application
    Filed: November 16, 2021
    Publication date: December 15, 2022
    Inventors: Chun-Wei Chang, Ming-Fa Chen, Chao-Wen Shih, Ting-Chu Ko
  • Publication number: 20220384314
    Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Patent number: 11515618
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 11516860
    Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: November 29, 2022
    Assignee: Pacesetter, Inc.
    Inventors: Yongjian Wu, Jyoti Bhayana, Chao-Wen Young, Tejpal Singh, Samir Shah
  • Publication number: 20220375793
    Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20220368005
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh