Abstract: Example implementations relate to power supply controllers. In some examples, a controller can include instructions to: set a power threshold for a power supply coupled to a computing component when the computing component is operating in a first state, determine when the computing component is alternating from the first state to a second state, and allow the power supply to exceed the power threshold for a fixed period of time in response to the computing component alternating from the first state to the second state.

Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.

Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.

Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.

Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Abstract: A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.

Abstract: A package includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a redistribution structure, an integrated circuit, an encapsulant, and conductive structures. The integrated circuit is disposed on the redistribution structure and includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate that extends continuously throughout the first chip. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate that extends continuously throughout the fourth chip. Sidewalls of the first chip are aligned with sidewalls of the fourth chip. The encapsulant laterally encapsulates the integrated circuit. The conductive structures penetrate through the encapsulant.

Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Abstract: A transfer system adaptable to performing levelling alignment includes a transfer head that picks up micro devices, the transfer head having a plurality of pick-up heads protruded from a bottom surface of the transfer head; and a levelling fixture configured to perform levelling alignment for the transfer head, the levelling fixture having a plurality of cavities that are concave downwards to correspondingly accommodate the pick-up heads respectively.

Abstract: A semiconductor device includes a semiconductor structure, a first dielectric layer and a plurality of multilayer stacks. The semiconductor structure includes conductive features therein. The first dielectric layer is on the semiconductor structure. The multilayer stacks are arranged on the first dielectric layer. Each of the multilayer stacks comprises a semiconductor layer over the first dielectric layer, a conductive layer over the semiconductor layer and a second dielectric layer over the conductive layer. The second dielectric layer includes a top portion and a bottom portion wider than the top portion.

Abstract: A network for neural pose transfer includes a pose feature extractor, and a style transfer decoder, wherein the pose feature extractor comprises a plurality of sequential extracting stacks, each extracting stack consists of a first convolution layer and an Instance Norm layer sequential to the first convolution layer. The style transfer decoder comprises a plurality of sequential decoding stacks, a second convolution layer sequential to the plurality of decoding stacks and a tan h layer sequential to the second convolution layer. Each decoding stack consists of a third convolution layer and a SPAdaIn residual block. A source pose mesh is input to the pose feature extractor, and an identity mesh is concatenated with the output of the pose feature extractor and meanwhile fed to each SPAdaIn residual block of the style transfer decoder. A system thereof is also provided.

Abstract: A coffee or tea brewing apparatus comprising a hollow cylinder with top and bottom openings, a permeable filter, a filter retaining ring which attaches to the bottom end of the hollow cylinder and encloses the bottom opening of the hollow cylinder with the permeable filter, a support ring to support the hollow cylinder above an open vessel, and a flexible lid. Coffee grounds or tea leaves are mixed with water inside the hollow cylinder which will then drain through the removable filter effectively separating any liquids into an open vessel while retaining undissolved solids within the hollow cylinder. The flexible lid may be used to enclose the top of the hollow cylinder and pressed on to produce a positive air pressure within the filter assembly to force the liquid through the permeable filter when a faster flow rate is desired.

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

Abstract: A light-emitting diode display is provided. The light-emitting diode display includes a substrate, a plurality of wires, a plurality of light-emitting areas, and at least one driver IC. The plurality of wires are formed on the substrate. The plurality of light-emitting areas include a light-emitting diode area and a virtual area. The plurality of light-emitting areas are arranged in a matrix. The virtual area of the plurality of light-emitting areas corresponds to each other. The driver IC is formed on the virtual area of the plurality of the light-emitting areas or on the plurality of the light-emitting areas.

Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.