Patents by Inventor Chao Wen

Chao Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11417629
    Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11404390
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chao Wen Wang
  • Publication number: 20220225879
    Abstract: Computer implemented methods and systems are provided that comprise, under control of one or more processors of a medical device, where the one or more processors are configured with specific executable instructions. The methods and systems include sensing circuitry configured to define a sensing channel to collect biological signals, memory configured to store program instructions, a processor configured to implement the program instructions to at least one of analyze the biological signals, manage storage of the biological signals or deliver a therapy, and communication circuitry configured to wirelessly communicate with at least one other implantable or external device, the communication circuitry configured to transition between a sleep state, a partial awake state and a fully awake state.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Yongjian Wu, Chao-Wen Young, Jun Yang, Reza Shahandeh, Gabriel A. Mouchawar
  • Patent number: 11393554
    Abstract: In one example, a device housing is described, which may include a base substrate and ion-exchanged glass beads disposed on an outer surface of the base substrate.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 19, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kuan-Ting Wu, Ya-Ting Yeh, Chao-Wen Cheng, Hsin-Yi Lee
  • Patent number: 11392530
    Abstract: In one example, an adapter card may include a circuit board having a male interface to be inserted into a discrete graphics card slot and a peripheral component interconnect express (PCIe) slot to communicatively couple a PCIe device. Further, the adapter card may include a voltage converter circuit disposed on the circuit board to convert a first voltage associated with the discrete graphics card slot to a second voltage corresponding to the PCIe device and a level shifter circuit disposed on the circuit board to modify a signal level in the discrete graphics card slot to a signal level in the PCIe device.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 19, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Po-Ying Chih, Chao-Wen Cheng, Chun-Yi Liu
  • Publication number: 20220214120
    Abstract: A heat sink includes a heat conduction portion and a heat dissipation portion. The heat conduction portion is a flat plate with two main surfaces parallel with each other and a plurality of side surfaces. One of the two main surfaces is a contacting surface contacting a heat source. The heat dissipation portion is extended outward from at least one of the plurality of side surfaces of the heat conduction portion. The heat dissipation portion includes a plurality of first branches and a plurality of second branches. Each of the first branches is a flat plate and has two opposite main surfaces and four side surfaces. The two opposite main surfaces of each of the first branches are parallel to the two main surfaces of the heat conduction portion. The second branches are extended from the first branches and parallel to the heat conduction portion.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Inventor: CHAO-WEN LU
  • Publication number: 20220184404
    Abstract: Methods and devices for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The methods and devices comprise storing, in memory in at least one of the IMD or the EI an advertising schedule defining a pattern for advertisement notices. The advertisement notices are distributed un-evenly and separated by unequal advertisement intervals. The method transmits, from a transmitter in at least one of the IMD or the EI the advertisement notices. The advertisement notices are distributed as defined by the advertising schedule. The method establishes a communication session between the IMD and the EI.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: Pacesetter, Inc.
    Inventors: Yongjian Wu, Samir Shah, Heidi Hellman, Reza Shahandeh, Tejpal Singh, Youjing Huang, Chao-Wen Young
  • Publication number: 20220189918
    Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20220181301
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 9, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20220182930
    Abstract: A method for managing power during communication with an implantable medical device, including establishing a communications link, utilizing a power corresponding to a session start power, to initiate a current session between an implantable medical device (IMD) and external device. A telemetry break condition of the communications link is monitored during the current session. The power utilized by the IMD is adjusted between low and high power levels, during the current session based on the telemetry break condition. The number of sessions is counted, including the current session and one or more prior sessions, in which the IMD utilized the higher power level, and a level for the session start power to be utilized to initiate a next session following the current session is adaptively learned based on the counting of the number of sessions.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Inventors: Perry Li, Lequan Zhang, Xing Pei, Jeffery Crook, Yongjian Wu, Jun Yang, Chao-Wen Young
  • Publication number: 20220179468
    Abstract: In examples, a computer system comprises a first power supply having first and second power rails; a second power supply having a third power rail; a motherboard coupled to the first power rail; a central processing unit (CPU) coupled to the second power rail; a variable performance electronic component coupled to the third power rail; and a controller coupled to enable inputs of the first and second power supplies.
    Type: Application
    Filed: July 25, 2019
    Publication date: June 9, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Chien-Fa Huang, Roger A. Pearson, Chung Yu Chang
  • Publication number: 20220171446
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, an unloaded component is detected. The unloaded component remains undetected upon completion of a boot process of the computing device. Thereafter, a power budget allocated to the unloaded component is determined. The power budget may be based on the thermal design power (TDP) of the computing device. Based on the power budget, a power configuration of the CPU is changed from a default power level to a high-performance power level, wherein the default power level corresponds to the TDP of the computing device and the high-performance power level is a power level above the default power level and upto a maximum power level of the CPU.
    Type: Application
    Filed: July 31, 2019
    Publication date: June 2, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Yen Tang Chang, Chao Wen Cheng, Chien Chen Su, Po Ying Chih
  • Patent number: 11348845
    Abstract: A bottom emission microLED display includes a microLED disposed above a transparent substrate; a light guiding layer surrounding the microLED to controllably guide light generated by the microLED towards the transparent substrate; and a reflecting layer formed over the light guiding layer to reflect the light generated by the microLED downwards and to confine the light generated by the microLED to prevent the light from leaking upwards or sidewards.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: May 31, 2022
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chao-Wen Wu
  • Patent number: 11335655
    Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Publication number: 20220147129
    Abstract: Techniques for reallocating power between a plurality of electronic components and a connection port of a computing system are described. In operation, operational state of an electronic component from amongst multiple electronic components is analysed. Based on the operational state of the electronic component, an unused power available with the electronic components is determined. Based on the availability of the unused power, a default power level associated with the connection port is increased, where the default power level is a predefined power allocated to the connection port for operation.
    Type: Application
    Filed: July 31, 2019
    Publication date: May 12, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chao Wen Cheng, Po Ying Chih, Yen Tang Chang
  • Publication number: 20220147127
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, a CPU is operated at default power level corresponding to a thermal design power (TDP) of the computing device. Thereafter, an unused power of the computing device is determined at run-time. The unused power is a difference between an allocated power budget of the component and current power consumption of the component, wherein the allocated power budget is an amount of power allocated to the component based on the TDP of the computing device. Based on the unused power the CPU is operated at a high-performance power level. The high-performance power level is a power level above the default power and up to a maximum power level of the CPU.
    Type: Application
    Filed: July 31, 2019
    Publication date: May 12, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Po Ying Chih, Chao Wen Cheng, Yen Tang Chang, Wei Chieh Liao, Yu Fan Chen, Chien Chen Su
  • Publication number: 20220140732
    Abstract: An example redundant power supply system comprises a power supply input to receive power from a power supply; a buck-boost converter coupled to the power supply input; and a controller coupled to the buck-boost converter. The controller is to receive a power supply identification signal from the power supply. The controller is also to enable or disable the buck-boost converter based on the power supply identification signal.
    Type: Application
    Filed: July 23, 2019
    Publication date: May 5, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Ying-Chi Chou, Feng Ming Lu, Chien Fa Huang, Chieh-Shen Huang, Tsung Yen Chen, Peter Seiler, Poying Chih
  • Publication number: 20220139882
    Abstract: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11322477
    Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11317803
    Abstract: Computer implemented methods and systems are provided that comprise, under control of one or more processors of a medical device, where the one or more processors are configured with specific executable instructions. The methods and systems include sensing circuitry configured to define a sensing channel to collect biological signals, memory configured to store program instructions, a processor configured to implement the program instructions to at least one of analyze the biological signals, manage storage of the biological signals or deliver a therapy, and communication circuitry configured to wirelessly communicate with at least one other implantable or external device, the communication circuitry configured to transition between a sleep state, a partial awake state and a fully awake state.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 3, 2022
    Assignee: Pacesetter, Inc.
    Inventors: Yongjian Wu, Chao-Wen Young, Jun Yang, Reza Shahandeh, Gabriel A. Mouchawar