Patents by Inventor Chao Zhao

Chao Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150221768
    Abstract: A method of manufacturing a semiconductor structure is disclosed. The method comprises: providing a substrate, forming a gate stack on the substrate and forming source/drain regions within the substrate; etching the source/drain regions to form trenches; forming a contact layer on the surface of the source/drain regions that have been etched; forming a stress material layer within the trenches; depositing an interlayer dielectric layer and forming contact plugs in contact with the stress material. Accordingly, a semiconductor structure is also disclosed.
    Type: Application
    Filed: September 17, 2012
    Publication date: August 6, 2015
    Inventors: Huicai Zhong, Qingqing Liang, Chao Zhao, Jun Luo
  • Publication number: 20150218617
    Abstract: The invention concerns methods for detecting a nucleic acid of interest in a solution comprising (a) contacting a solution suspected of containing the nucleic acid of interest with a PNA capture probe and a PNA reporter probe; wherein (i) the PNA capture probe comprises at least two trans-cyclopentanes; (ii) the PNA reporter probe comprises at least six biotin groups; (iii) the PNA capture probe bound to a surface; and (iv) the PNA capture probe and the PNA reporter probe each comprise a nucleobase sequence that is complementary to different non-overlapping portions of the nucleic acid of interest; (b) detecting the presence of the PNA capture probe and the PNA reporter probe bound to the surface; wherein the nucleic acid of interest is detected when 1-1000 molecules of the nucleic acid of interest are present in the solution being tested.
    Type: Application
    Filed: August 16, 2013
    Publication date: August 6, 2015
    Inventors: Daniel H. Appella, Christopher Micklitsch, Bereket Yemane, Chao Zhao
  • Publication number: 20150214332
    Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.
    Type: Application
    Filed: November 13, 2012
    Publication date: July 30, 2015
    Inventors: Chunlong Li, Junfeng Li, Jiang Yan, Lingkuan Meng, Xiaobin He, Guanglu Chen, Chao Zhao
  • Patent number: 9070719
    Abstract: A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: June 30, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Jun Luo, Chao Zhao
  • Patent number: 9049061
    Abstract: This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: June 2, 2015
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Qiuxia Xu, Chao Zhao, Gaobo Xu
  • Patent number: 9024435
    Abstract: A semiconductor device, a formation method thereof, and a package structure are provided. The semiconductor device comprises: a semiconductor substrate in which a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed; a dielectric layer, provided on the semiconductor substrate and covering the MOSFET, wherein a plurality of interconnection structures are formed in the dielectric layer; and at least one heat dissipation path, embedded in the dielectric layer between the interconnection structures, for liquid or gas to circulate in the heat dissipation path, wherein openings of the heat dissipation path are exposed on the surface of the dielectric layer. The present invention can improve heat dissipation efficiency, and prevent chips from overheating.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: May 5, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Jiang Yan, Chao Zhao
  • Patent number: 9012965
    Abstract: The invention discloses a novel MOSFET device fabricated by a gate last process and its implementation method, the device comprising: a substrate; a gate stack structure located on a channel region in the substrate, on either side of which is eliminated the conventional isolation spacer; an epitaxially grown ultrathin metal silicide constituting a source/drain region. Wherein the device eliminates the high resistance region below the conventional isolation spacer; a dopant segregation region with imlanted ions is formed between the source/drain and the channel region, which decreases the Schottky barrier height between the metal silicide source/drain and the channel. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: April 21, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jun Luo, Chao Zhao
  • Patent number: 8994119
    Abstract: The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: March 31, 2015
    Assignee: The Institute of Microelectronics Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Zuozhen Fu, Qiuxia Xu, Chao Zhao, Dapeng Chen
  • Patent number: 8987127
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 24, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jun Luo, Chao Zhao, Huicai Zhong, Junfeng Li, Dapeng Chen
  • Publication number: 20150035087
    Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.
    Type: Application
    Filed: December 12, 2012
    Publication date: February 5, 2015
    Inventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao
  • Patent number: 8946071
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 3, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jun Luo, Chao Zhao, Huicai Zhong, Junfeng Li, Dapeng Chen
  • Publication number: 20140377056
    Abstract: An air shield apparatus includes a bracket, a number of baffles, and a connecting member. The bracket includes two opposite side plates. Each baffle includes a blocking piece placed between the side plates of the bracket, and a shaft located at a first side of the blocking piece. The shafts are rotatably connected to the side plates of the bracket. The connecting member includes a connecting pole and a number of pivot portions pivotably connected to the baffles.
    Type: Application
    Filed: March 21, 2014
    Publication date: December 25, 2014
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: XIAO-FENG MA, CHAO ZHAO
  • Publication number: 20140357027
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region.
    Type: Application
    Filed: March 23, 2012
    Publication date: December 4, 2014
    Inventors: Jun Luo, Chao Zhao, Huicai Zhong, Junfeng Li, Dapeng Chen
  • Publication number: 20140332958
    Abstract: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer ?-Si. Correspondingly, a dummy gate in a gate-last process is also provided.
    Type: Application
    Filed: December 12, 2012
    Publication date: November 13, 2014
    Inventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao
  • Publication number: 20140321037
    Abstract: A dummy server chassis to block an idle opening in a cabinet server includes a first blocking member and a second blocking member. The first blocking member covers the idle opening, and the second blocking member covers a lower server unit adjacent to the idle opening. The second blocking member includes a bracket extending from a side of the first blocking member, and a covering plate mounted to the bracket.
    Type: Application
    Filed: August 27, 2013
    Publication date: October 30, 2014
    Applicants: Hon Hai Precision Industry Co., Ltd., Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd
    Inventor: CHAO ZHAO
  • Publication number: 20140302644
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate.
    Type: Application
    Filed: March 23, 2012
    Publication date: October 9, 2014
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Jun Luo, Chao Zhao, Huicai Zhong, Junfeng Li, Dapeng Chen
  • Publication number: 20140273426
    Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.
    Type: Application
    Filed: December 12, 2012
    Publication date: September 18, 2014
    Inventors: Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao
  • Patent number: 8816326
    Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: August 26, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Jun Luo, Chao Zhao, Honggang Liu, Dapeng Chen
  • Publication number: 20140227878
    Abstract: A method for manufacturing a small-size fin-shaped structure, comprising: forming a first mask layer and a second mask layer on a substrate in sequence; etching the first mask layer and the second mask layer to form a hard mask pattern, wherein a second mask layer pattern is wider than a first mask layer pattern; eliminating the second mask layer pattern; and performing a dry etching of the substrate by taking the first mask layer pattern as a mask, so as to form a fin-shaped structure. According to the method for manufacturing a small-size fin-shaped structure of the present invention, firstly a large-size hard mask is prepared, then a width controllable small-size hard mask is prepared through a wet corrosion, and finally the bulk silicon wafer is etched, so as to obtain the required small-size fin-shaped structure, thereby improving the electrical properties and the integration level of the device, simplifying the processes and reducing the cost.
    Type: Application
    Filed: March 5, 2012
    Publication date: August 14, 2014
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Tao Yang, Chao Zhao, Junfeng Li, Yihong Lu
  • Patent number: 8802518
    Abstract: A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 12, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Wenwu Wang, Chao Zhao, Kai Han, Dapeng Chen