Patents by Inventor Chao Zhao

Chao Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180087722
    Abstract: Embodiments of the present disclosure describe a white light illumination system using InGaN-based orange nanowires (NWs) LED, in conjunction with a blue LD for high speed optical wireless communications. By changing the relative intensities of an ultrabroad linewidth orange LED and narrow-linewidth blue LD components, a hybrid LED/LD device achieves correlated color temperature (CCT) ranging from 3000 K to above 6000K with color rendering index (CRI) values reaching 83.1.
    Type: Application
    Filed: August 10, 2017
    Publication date: March 29, 2018
    Inventors: Boon S. OOI, Bilal JANJUA, Chao SHEN, Chao ZHAO, Tien Khee NG
  • Patent number: 9899270
    Abstract: There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffu
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 20, 2018
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Gaobo Xu, Huajie Zhou, Qingqing Liang, Dapeng Chen, Chao Zhao
  • Publication number: 20180045667
    Abstract: A sensing device is disclosed. The sensing device comprises: a first electrode layer, a second electrode layer, which are separated by a dielectric layer; and through holes penetrating through the first electrode layer, the second electrode layer and the dielectric layer.
    Type: Application
    Filed: August 3, 2015
    Publication date: February 15, 2018
    Inventors: Chengjun Huang, Jun Luo, Chao Zhao
  • Publication number: 20180040977
    Abstract: An electrical connector (100) includes: an insulative housing having a base (11) and a pair of side walls (12), each side wall having a resilient inner arm (121) and a stationary outer arm (122); and plural contacts (2) retained to the insulative housing, wherein the resilient inner arm extends along a horizontal, front-to-back direction and has a front end operable in both a vertical, top-to-bottom direction and the horizontal, front-to-back direction to move toward the stationary outer arm.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 8, 2018
    Inventors: Yue-Chao ZHAO, Zhi-Jian CHEN, Lai-Ang HU
  • Patent number: 9877273
    Abstract: The present invention provides a D2D communication method, a terminal, and a network device. The method includes: acquiring, by a first terminal, network information, where the network information includes a system message sent by a network device and/or a cell coverage result; determining, by the first terminal according to the network information, whether to enable D2D communication for autonomously discovering a second terminal; and if the first terminal determines to enable the D2D communication, discovering, by the first terminal, the second terminal autonomously, and performing the D2D communication with the second terminal directly.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: January 23, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Bo Lin, Chao Zhao
  • Publication number: 20170365482
    Abstract: The present invention provides a method for growing ni-containing thin film with single atomic layer deposition technology, comprising steps of: A) placing a substrate in a reaction chamber, and under the vacuum condition, passing a gas-phase Ni source in a form of pulses into the reaction chamber for deposition to obtain a substrate deposited with the Ni source, the Ni source comprising a compound having a structure of Formula I; B) passing a gas-phase reducing agent in a form of pulses into the reaction chamber to reduce the Ni source deposited on the substrate, obtaining a substrate deposited with a Ni thin film. The application of the Ni source having a structure of Formula I in the single atomic layer deposition technology allows a Ni-containing deposition layer with good shape retention to be deposited and formed on a nano-sized semiconductor device.
    Type: Application
    Filed: December 1, 2016
    Publication date: December 21, 2017
    Inventors: Yuqiang DING, Liyong DU, Yuxiang ZHANG, Chao ZHAO, Jinjuan XIANG
  • Publication number: 20170327944
    Abstract: Provided is an aluminum precursor for thin-film deposition having a structure of formula (I) or (II), wherein R1, R2, R3, R4, R5, R6, and R7 each independently represent a hydrogen atom, C1˜C6 alkyl, halo-C1˜C6 alkyl, C2˜C5 alkenyl, halo-C2˜C5 alkenyl, C3˜C10 cycloalkyl, halo-C3˜C10 cycloalkyl, C6˜C10 aryl, halo-C6˜C10 aryl or —Si(R0)3, and wherein R0 is C1˜C6 alkyl or halo-C1˜C6 alkyl. According to the present invention, based on the interaction principle between molecules, aluminum precursors for thin-film deposition are provided, which have a good thermal stability, are not susceptible to decomposition and convenient for storage and transportation, have good volatility at a high temperature, and are excellent in film formation.
    Type: Application
    Filed: September 17, 2015
    Publication date: November 16, 2017
    Inventors: Yuqiang DING, Chao ZHAO, Chongying XU, Shuyan YANG, Jinjuan XIANG, Hongyan MIAO, Dawei WANG
  • Publication number: 20170309736
    Abstract: A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.
    Type: Application
    Filed: December 2, 2016
    Publication date: October 26, 2017
    Inventors: Sen HUANG, Xinyu LIU, Xinhua WANG, Ke WEI, Qilong BAO, Wenwu WANG, Chao ZHAO
  • Publication number: 20170294478
    Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m?1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.
    Type: Application
    Filed: April 3, 2017
    Publication date: October 12, 2017
    Inventors: Hushan CUI, Jinjuan XIANG, Xiaobin HE, Tao YANG, Junfeng LI, Chao ZHAO
  • Patent number: 9773707
    Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 26, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Guilei Wang, Jinbiao Liu, Jianfeng Gao, Junfeng Li, Chao Zhao
  • Publication number: 20170263452
    Abstract: A method for manufacturing a two-dimensional material structure and a resultant two-dimensional material device. The method comprises steps of: forming a sacrificial FIN structure on a substrate; covering the sacrificial FIN structure with a dielectric; releasing the sacrificial FIN structure; forming a carrier FIN structure at a position for releasing the sacrificial FIN; and self-restrictedly growing two-dimensional material structure by taking the carrier FIN structure as a substrate. Utilizing the sacrificial FIN structure to implement self-restrictedly growing of the nanometer structure of the two-dimensional material results in a high precision, lower edge roughness, high yields and low process deviation as well as compatibility with the processing of CMOS large scale integrated circuits, making the method suitable for a large scale production of the two-dimensional material and related devices.
    Type: Application
    Filed: September 9, 2016
    Publication date: September 14, 2017
    Inventors: Yajuan SU, Kunpeng JIA, Chao ZHAO, Jun ZHAN, Heshi CAO
  • Publication number: 20170205330
    Abstract: A particle screening device is provided. The particle screening device comprises: a substrate including a first side and a second side opposite to the first side; a micropore array formed on the substrate, wherein each micropore penetrates through the substrate from the first side to the second side and has a size configured to at least permit particles smaller than target particles flow through; and electrodes formed on at least one side of the first and second sides of the substrate and around at least some micropores, wherein the electrodes are configured to generate an electric field at corresponding micropores.
    Type: Application
    Filed: June 24, 2015
    Publication date: July 20, 2017
    Applicant: Ocular Fluidics, Inc.
    Inventors: Chengjun Huang, Jun Luo, Chao Zhao
  • Publication number: 20170151574
    Abstract: The present disclosure provides a cell positioning unit, array, device and a method for manufacturing the same. The cell positioning unit comprises: a substrate; at least a pair of microelectrodes on the substrate, wherein the microelectrodes are disposed at intervals on a circumference such that pDEP force are generated in an area where tips of the microelectrodes aggregate, and wherein a voltage signal applied to at least one microelectrode has a phase difference with a voltage signal applied to another microelectrode; and a cell positioning hole on the microelectrodes, wherein the cell positioning hole has an accommodation space which exposes the pDEP force fields and accommodates a single cell. By applying an AC voltage signal having a certain amplitude, frequency and phase to the microelectrodes, cells will move to surfaces of the microelectrodes, such that a single cell can be accurately positioned to a certain place by means of the cell positioning hole and the microelectrodes.
    Type: Application
    Filed: June 23, 2015
    Publication date: June 1, 2017
    Inventors: Chengjung Huang, Jun Luo, Chao Zhao
  • Publication number: 20170120248
    Abstract: Disclosed herein are apparatuses comprising, for example, a microfluidic channel device comprising a main body comprising a channel configured to provide for helical fluid motion of material within the channel; and a temperature control system that applies a temperature gradient to the channel. Methods of making and using the apparatus are also described.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 4, 2017
    Inventors: Xuanhong Cheng, Chao Zhao, Alparslan Oztekin
  • Publication number: 20170104081
    Abstract: A method for preparing a TiAl alloy thin film, wherein a reaction chamber is provided, in which at least one substrate is placed; an aluminum precursor and a titanium precursor are introduced into the reaction chamber, wherein the aluminum precursor has a molecular structure of a structural formula (I); and the aluminum precursor and the titanium precursor are brought into contact with the substrate so that a titanium-aluminum alloy thin film is formed on the surface of the substrate by vapor deposition. The method solves the problem of poor step coverage ability and the problem of incomplete filling with regard to the small-size devices by the conventional methods. Meanwhile, the formation of titanium-aluminum alloy thin films with the aid of plasma is avoided so that the substrate is not damaged by plasma.
    Type: Application
    Filed: June 6, 2016
    Publication date: April 13, 2017
    Inventors: Yuqiang DING, Chao ZHAO, Jinjuan XIANG
  • Patent number: 9589809
    Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: March 7, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiang Xu, Chao Zhao, Jun Luo, Guilei Wang, Tao Yang, Junfeng Li
  • Publication number: 20170000039
    Abstract: This present invention discloses an integrated method of cyclic utilization of energy grasses comprising the steps of generating biogas residue from the energy grasses, growing edible mushrooms from the biogas residue, producing livestock or poultry feeds from the spent mushroom culture medium, feeding livestock with the feeds, and producing organic fertilizers from the manure of the livestock or poultry. The method, by producing biogas, edible mushrooms, feeds, livestock or poultry, and organic fertilizers, makes an integrated and cyclic use of energy grasses and aforementioned products. This invention will help achieve the goal of cyclic use of energy grasses with great efficiency.
    Type: Application
    Filed: January 22, 2015
    Publication date: January 5, 2017
    Applicant: FUJIAN AGRICULTURE AND FORESTRY UNIVERSITY
    Inventors: Bin LIU, Zheng XIAO, Chao ZHAO, Yifan HUANG
  • Publication number: 20160379829
    Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.
    Type: Application
    Filed: August 28, 2015
    Publication date: December 29, 2016
    Inventors: Guilei Wang, Jinbiao Liu, Jianfeng Gao, Junfeng Li, Chao Zhao
  • Publication number: 20160268124
    Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.
    Type: Application
    Filed: August 7, 2015
    Publication date: September 15, 2016
    Inventors: Xinyu Liu, Sen Huang, Xinhua Wang, Ke Wei, Wenwu Wang, Junfeng Li, Chao Zhao
  • Patent number: 9425288
    Abstract: A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: August 23, 2016
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Chao Zhao