Abstract: The present disclosure provides a cell positioning unit, array, device and a method for manufacturing the same. The cell positioning unit comprises: a substrate; at least a pair of microelectrodes on the substrate, wherein the microelectrodes are disposed at intervals on a circumference such that pDEP force are generated in an area where tips of the microelectrodes aggregate, and wherein a voltage signal applied to at least one microelectrode has a phase difference with a voltage signal applied to another microelectrode; and a cell positioning hole on the microelectrodes, wherein the cell positioning hole has an accommodation space which exposes the pDEP force fields and accommodates a single cell. By applying an AC voltage signal having a certain amplitude, frequency and phase to the microelectrodes, cells will move to surfaces of the microelectrodes, such that a single cell can be accurately positioned to a certain place by means of the cell positioning hole and the microelectrodes.

Abstract: Disclosed herein are apparatuses comprising, for example, a microfluidic channel device comprising a main body comprising a channel configured to provide for helical fluid motion of material within the channel; and a temperature control system that applies a temperature gradient to the channel. Methods of making and using the apparatus are also described.

Abstract: A method for preparing a TiAl alloy thin film, wherein a reaction chamber is provided, in which at least one substrate is placed; an aluminum precursor and a titanium precursor are introduced into the reaction chamber, wherein the aluminum precursor has a molecular structure of a structural formula (I); and the aluminum precursor and the titanium precursor are brought into contact with the substrate so that a titanium-aluminum alloy thin film is formed on the surface of the substrate by vapor deposition. The method solves the problem of poor step coverage ability and the problem of incomplete filling with regard to the small-size devices by the conventional methods. Meanwhile, the formation of titanium-aluminum alloy thin films with the aid of plasma is avoided so that the substrate is not damaged by plasma.

Abstract: A method of depositing a tungsten (W) layer is disclosed. In one aspect, the method includes depositing a SiH4 base W film on a surface of a substrate to preprocess the surface. The method includes depositing a B2H6 base W layer on the preprocessed surface. The SiH4 base W film may be several atom layers thick. The film and base W layer may be deposited in a single ALD process, include reactive gas soak, reactive gas introduction, and main deposition operations. Forming the film may include introducing SiH4 gas into a reactive cavity during the gas soak operation, and introducing SiH4 and WF6 gas into the cavity during the gas introduction operation. The SiH4 and WF6 gases may be alternately introduced, for a number of cycles depending on the thickness of the tungsten layer to be deposited.

Abstract: This present invention discloses an integrated method of cyclic utilization of energy grasses comprising the steps of generating biogas residue from the energy grasses, growing edible mushrooms from the biogas residue, producing livestock or poultry feeds from the spent mushroom culture medium, feeding livestock with the feeds, and producing organic fertilizers from the manure of the livestock or poultry. The method, by producing biogas, edible mushrooms, feeds, livestock or poultry, and organic fertilizers, makes an integrated and cyclic use of energy grasses and aforementioned products. This invention will help achieve the goal of cyclic use of energy grasses with great efficiency.

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.

Abstract: A method for manufacturing a low interface state device includes performing a remote plasma surface process on a III-Nitride layer on a substrate; transferring the processed substrate to a deposition cavity via an oxygen-free transferring system; and depositing on the processed substrate in the deposition cavity. The deposition may be low pressure chemical vapor deposition (LPCVD). The interface state between a surface dielectric and III-Nitride material may be significantly decreased by integrating a low impairment remote plasma surface process and LPCVD.

Abstract: A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.

Abstract: One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.

Abstract: In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.

Abstract: An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a transfer chamber provided with a mechanical manipulator for transferring the wafer; an etching chamber for removing a natural oxide layer on the surface of the wafer and provided with a graphite base for positioning the wafer; at least one epitaxial reaction chamber; a gas distribution device for supplying respective gases to the primary chamber, the wafer loading chamber, the transfer chamber, the etching chamber and the epitaxial reaction chamber; and a vacuum device. The wafer loading, transfer, etching, and epitaxial reaction chambers are all positioned within the primary chamber. The apparatus integrates the etching chamber and epitaxial reaction chamber to remove the natural oxide layer on the surface of the wafer in a condition of isolating water and oxygen before the epitaxial reaction has occurred.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine.

Abstract: In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract: Embodiments of the present invention relate to the communications field, and disclose a method for uplink data transmission, a terminal, and a wireless communication node, which can ensure that a HARQ mechanism between a terminal and a wireless communication node works normally. The method includes: determining, by a first wireless communication node, whether a terminal is within downlink coverage of a second wireless communication node; and when the first wireless communication node determines that the terminal is not within the downlink coverage of the second wireless communication node, instructing, by the first wireless communication node, the terminal to use a non-feedback mode; and/or instructing, by the first wireless communication node, the second wireless communication node to use a non-feedback mode.

Abstract: The present invention provides a method for manufacturing a semiconductor device, which comprises: providing an SOI substrate, which comprises a base layer, an insulating layer located on the base layer and a active layer located on the insulating layer; forming a gate stack on the SOI substrate; etching the active layer, the insulating layer and a part of the base layer of the SOI substrate with the gate stack as a mask, so as to form trenches on both sides of the gate stack; forming a crystal dielectric layer within the trenches, wherein the upper surface of the crystal dielectric layer is lower than the upper surface of the insulating layer and not lower than the lower surface of the insulating layer; and forming source/drain regions on the crystal dielectric layer. The present invention further provides a semiconductor device.

Abstract: A wireless communications method, user equipment, and a network node are disclosed. The method includes: receiving, by user equipment, a message sent by a first network node, where the message includes measurement instruction information and connection indication information; measuring, by the user equipment in the RRC-IDLE mode, the neighboring cells according to the measurement instruction information, and obtaining measurement results; and selecting, by the user equipment, at least one to-be-connected cell from the neighboring cells according to the connection indication information and the measurement results, and keeping camping on the cell of the first network node when the user equipment is in the RRC-IDLE mode. Embodiments of the present invention can advance a time at which a new cell is found.

Abstract: A method of forming a hybrid physically and chemically cross-linked double-network hydrogel with highly recoverable and mechanical properties in a single-pot synthesis is provided. The method comprises the steps of combining the hydrogel precursor reactants into a single pot. The hydrogel precursor reactants include water; a polysaccharide; a methacrylate monomer; an ultraviolet initiator; and a chemical crosslinker. Next the hydrogel precursor reactants are heated to a temperature higher than the melting point of the polysaccharide and this temperature is retained until the polysaccharide is in a sol state. Then the single-pot is cooled to a temperature lower than the gelation point of the polysaccharide and this temperature is retained to form a first network. Thereafter, photo-initiated polymerization of the methacrylate monomer occurs via the ultraviolet initiator to form the second network.