Abstract: Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an integrated circuit includes providing an integrated circuit comprising an inner lead bondpad. A first insulative passivation layer is formed over the integrated circuit. A bondpad-redistribution line is formed over the first insulative passivation layer and in electrical connection with the inner lead bondpad through the first insulative passivation layer. The bondpad-redistribution line includes an outer lead bondpad area. A second insulative passivation layer is formed over the integrated circuit and the bondpad-redistribution line. The second insulative passivation layer is formed to have a sidewall outline at least a portion of which is proximate to and conforms to at least a portion of the bondpad-redistribution line. Other aspects and implementations are contemplated.

Abstract: A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the die, forming a plurality of interconnect contacts on the redistribution contacts, and forming an insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming terminal contacts on the interconnect contacts, or alternately forming conductors in electrical communication with the interconnect contacts and then forming terminal contacts in electrical communication with the conductors.

Abstract: A method of packaging at least a portion of a semiconductor die or dice is disclosed. Uncured material may be disposed proximate at least the periphery of at least one semiconductor die and at least partially cured substantially as a whole. Methods of forming conductive elements such as traces, vias, and bond pads are also disclosed. More specifically, forming at least one organometallic layer to a substrate surface and selectively heating at least a portion thereof is disclosed. Also, forming a layer of conductive photopolymer over at least a portion of a surface of a substrate and removing at least a portion thereof is disclosed. A microlens having a plurality of mutually adhered layers of cured, optically transmissive material, methods of forming same, and systems so equipped are disclosed.

Abstract: Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Abstract: Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method comprises providing a workpiece including a substrate having a plurality of microelectronic dies on and/or in the substrate. The individual dies include integrated circuitry and pads electrically coupled to the integrated circuitry. The method then includes depositing an underfill layer onto a front side of the substrate. The method also includes selectively forming apertures in the underfill layer to expose the pads at the front side of the substrate. The method further includes depositing a conductive material into the apertures and in electrical contact with the corresponding pads. In one aspect of this embodiment, the underfill layer is a photoimageable material.

Abstract: Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.

Abstract: A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating layer. The component also includes terminal contacts formed on tip portions of the interconnect contacts. Alternately the component can include conductors and bonding pads in electrical communication with the interconnect contacts configured to redistribute the pattern of the die contacts. A method for fabricating the component includes the steps of forming the interconnect contacts on the die contacts, and forming the insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming the terminal contacts on the interconnect contacts, or alternately forming the conductors and bonding pads in electrical communication with the interconnect contacts and then forming the terminal contacts on the bonding pads.

Abstract: Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover that are electrically coupled to corresponding bond-pads of the die. The interconnects provide external electrical contacts for the bond-pads of the die. The interconnects can extend through the cover or along a surface of the cover.

Abstract: An electrical contact for use with a semiconductor device, a carrier, a probe card, or another substrate includes a dielectric core and a conductive coating on at least a portion thereof. Alternatively, an electrical contact may include a plurality of adjacent, mutually adhered regions comprising conductive material. The electrical contact may be rigid or flexible and resilient. Protective structures for use with flexible resilient contacts prevent deformation of such contacts beyond their elastic limits.

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.

Abstract: A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least another portion integral with the fixed portion, laterally unsupported within a thickness of the substrate and extending beyond a side thereof. Dual-sided compliant contact structures, methods of forming compliant contact structures, a method of testing a semiconductor device and a testing system are also disclosed.

Abstract: Conductive or semiconductive binders, both inorganic and organic, are used for providing sufficient binding action to hold powder phosphor particles together, as well as to the glass screen of a field emission display device.

Abstract: A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating layer. The component also includes terminal contacts formed on tip portions of the interconnect contacts. Alternately the component can include conductors and bonding pads in electrical communication with the interconnect contacts configured to redistribute the pattern of the die contacts. A method for fabricating the component includes the steps of forming the interconnect contacts on the die contacts, and forming the insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming the terminal contacts on the interconnect contacts, or alternately forming the conductors and bonding pads in electrical communication with the interconnect contacts and then forming the terminal contacts on the bonding pads.

Abstract: A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating layer. The component also includes terminal contacts formed on tip portions of the interconnect contacts. Alternately the component can include conductors and bonding pads in electrical communication with the interconnect contacts configured to redistribute the pattern of the die contacts. A method for fabricating the component includes the steps of forming the interconnect contacts on the die contacts, and forming the insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming the terminal contacts on the interconnect contacts, or alternately forming the conductors and bonding pads in electrical communication with the interconnect contacts and then forming the terminal contacts on the bonding pads.

Abstract: A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating layer. The component also includes terminal contacts formed on tip portions of the interconnect contacts. Alternately the component can include conductors and bonding pads in electrical communication with the interconnect contacts configured to redistribute the pattern of the die contacts. A method for fabricating the component includes the steps of forming the interconnect contacts on the die contacts, and forming the insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming the terminal contacts on the interconnect contacts, or alternately forming the conductors and bonding pads in electrical communication with the interconnect contacts and then forming the terminal contacts on the bonding pads.

Abstract: A high resolution field emission display includes a faceplate and a baseplate. The faceplate includes a transparent viewing layer, a transparent conductive layer formed on the transparent viewing layer and intersecting stripes of light-absorbing, opaque insulating material formed on the transparent conductive layer. The insulating material defines openings less than one hundred microns wide between the intersecting stripes. The faceplate also includes a plurality of localized regions of cathodoluminescent material, each formed in one of the openings. The cathodoluminescent material includes a metal oxide providing reduced resistivity in the cathodoluminescent material. Significantly, the reduced resistivity of the cathodoluminescent material together with the focusing effect of the insulating material provide increased acuity in luminous images formed on the faceplate.

Abstract: Binders, both inorganic and organic, are used for providing sufficient binding action to hold powder phosphor particles together as well as to the glass screen of a field emission display device.

Abstract: A high resolution field emission display includes a faceplate and a baseplate. The faceplate includes a transparent viewing layer, a transparent conductive layer formed on the transparent viewing layer and intersecting stripes of light-absorbing, opaque insulating material formed on the transparent conductive layer. The insulating material defines openings less than one hundred microns wide between the intersecting stripes. The faceplate also includes a plurality of localized regions of cathodoluminescent material, each formed in one of the openings. The cathodoluminescent material includes a metal oxide providing reduced resistivity in the cathodoluminescent material. Significantly, the reduced resistivity of the cathodoluminescent material together with the focusing effect of the insulating material provide increased acuity in luminous images formed on the faceplate.

Abstract: A high resolution field emission display includes a faceplate and a baseplate. The faceplate includes a transparent viewing layer, a transparent conductive layer formed on the transparent viewing layer and intersecting stripes of light-absorbing, opaque insulating material formed on the transparent conductive layer. The insulating material defines openings less than one hundred microns wide between the intersecting stripes. The faceplate also includes a plurality of localized regions of cathodoluminescent material, each formed in one of the openings. The cathodoluminescent material includes a metal oxide providing reduced resistivity in the cathodoluminescent material. Significantly, the reduced resistivity of the cathodoluminescent material together with the focusing effect of the insulating material provide increased acuity in luminous images formed on the faceplate.