Patents by Inventor Che-An Lee

Che-An Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230375821
    Abstract: A head up display device includes an image generation unit, an imaging unit, an infrared light splitting element, and at least one infrared light detecting element. The infrared light splitting element is located on a transmission path of at least one ambient light beam, and configured to split an infrared light beam from the at least one ambient light beam. The at least one infrared light detecting element is located on a transmission path of the infrared light beam of the at least one ambient light beam, and configured to detect light intensity of the infrared light beam. When the at least one infrared light detecting element detects that the light intensity of the infrared light beam exceeds a predetermined threshold, the head up display device reduces light intensity of a portion of the at least one ambient light beam transmitted to the image generation unit.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 23, 2023
    Applicant: Coretronic Corporation
    Inventors: Po-Che Lee, Shih-Yi Lin
  • Publication number: 20230373018
    Abstract: In some embodiments, the present disclosure relates to a method that includes bonding a first wafer to a second wafer to form a wafer stack and removing a top portion of the second wafer. A first trim blade having a first blade width is aligned over the second wafer. The first trim blade is used to form a trench that separates a central portion of the second wafer from a peripheral portion of the second wafer. The trench is arranged at a first distance from an outer perimeter of the second wafer, and extends from a top surface of the second wafer to a trench depth beneath the top surface of the first wafer. A second trim blade having a second blade width is aligned over the peripheral portion, the second blade width being greater than the first blade width. The peripheral portion is removed using the second trim blade.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Ping-Tzu Chen
  • Publication number: 20230366833
    Abstract: A semiconductor device inspection method including: depositing a dielectric material over a substrate to form an interconnect-level dielectric (ILD) layer; patterning the ILD layer to form via structures in the ILD layer; depositing an electrically conductive material to form an inspection layer on the ILD layer and in the via structures; imaging the inspection layer to generate image data; and detecting any defects in the via structures by analyzing the image data.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: I-Che Lee, Huai-Ying Huang
  • Publication number: 20230368028
    Abstract: Features related to systems and methods for automated generation of a machine learning model based in part on a pretrained model are described. The pretrained model is used as a starting point to augment and retrain according to client specifications. The identification of an appropriate pretrained model is based on the client specifications such as model inputs, model outputs, and similarities between the data used to train the models.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 16, 2023
    Inventors: Hagay Lupesko, Anirudh Acharya, Cheng-Che Lee, Lai Wei, Kalyanee Chendke, Ankit Khedia, Vandana Kannan, Sandeep Krishnamurthy, Roshani Nagmote
  • Publication number: 20230369215
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Patent number: 11814825
    Abstract: A telescopic structure of a faucet having a movable tube contains: a body, a water supply tube, a movable tube, a spring, and a depressurization element. The body includes a screwing portion, a coupling portion, and a water outlet. The water supply includes an upright extension and an opening. The movable tube includes a slide portion and a water head engaged with the opening of the water supply tube and is pulled with the movable tube based on using requirements. The spring is accommodated in the upright extension and is fitted on the movable tube. The depressurization element includes a first face, a second face opposite to the first face, a peripheral face defined between and connected with the first face and the second face, and multiple flowing apertures defined proximate to a center of the depressurization element and communicating with the first face and the second face.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: November 14, 2023
    Assignee: Ching Shenger Co., Ltd.
    Inventors: Chin-Tsai Lee, Ming-Che Lee
  • Publication number: 20230356545
    Abstract: A hub device is provided, including: a hub shell, defining an axial direction, including a room open in the axial direction, an inner wall of the room including an annular toothed portion and an annular trench; a ratchet ring, including an outer toothed portion, the ratchet ring being disposed in the room, the outer toothed portion and the annular toothed portion being engaged with each other; and a blocking member, disposed within the annular trench, the blocking member and the ratchet ring being blocked with each other in the axial direction.
    Type: Application
    Filed: April 10, 2023
    Publication date: November 9, 2023
    Inventor: Chung-Che LEE
  • Publication number: 20230360976
    Abstract: Various embodiments of the present disclosure are directed towards a method for nondestructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
  • Patent number: 11799221
    Abstract: A fan connector structure is applicable to a system circuit board having a circuit board-end connector provided thereon and includes a fan having a fan frame main body and a fan-end connector projected from an outer side of the fan frame main body. The fan-end connector and the fan frame main body can be selectively integrally or non-integrally formed with each other. The fan-end connector is correspondingly connectable to the circuit board-end connector, so as to realize the purpose of automated and quick assembling of the fan to the system circuit board with less labor and time cost.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 24, 2023
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Sung-Wei Sun, Ming-Che Lee
  • Patent number: 11790172
    Abstract: The disclosure relates to systems and methods for identifying entities related to a task in a natural language input. An entity detection model is provided which receives a natural language input. The entity detection model processes the natural language input using an entity encoder and an input encoder. The entity encoder identifies and encodes relevant entities while the input encoder generates a contextual encoding which represents contextual information associated with a relevant entity. The encoded entity and contextual encodings may then be combined and processed to generate a probability score for an identified entity. A negation constraint model is also disclosed. The negation constraint model receives the natural language input and the identified entities. The natural language input is analyzed to identify negation cues and determine if the negation cue is associated with an identified entity.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 17, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pamela Bhattacharya, Barun Patra, Chala Fekadu Fufa, Charles Yin-Che Lee
  • Publication number: 20230325738
    Abstract: A system and method for allocating a recurring resource is described. The system receives a request to allocate the recurring resource of an application to computing devices associated with one or more users. The system identifies a cadence of the recurring resource and a range based on the cadence. A period is determines based on the cadence and the range. The system accesses user resource data of the application for each period and iteratively computes a resource availability score for the period based on the corresponding user resource data. The system determines that the resource availability score of an instance of the period is less than a threshold value and allocates the recurring resource to instances of the period where the corresponding resource availability score exceeds the threshold value.
    Type: Application
    Filed: August 31, 2021
    Publication date: October 12, 2023
    Inventors: Warren David Johnson III, Charles Yin-Che LEE, Xi DENG
  • Publication number: 20230327137
    Abstract: The present invention provides a manufacturing method of an electrode. The method includes steps of: mixing a first catalyst with a first average particle size, a second catalyst with a second average particle size, a first conductive agent, a first adhesive, and a solvent to form a first mixture, wherein a weight ratio of the first catalyst to the second catalyst is 5:1 to 1:5; stirring the first mixture to obtain a second mixture; rolling the second mixture into a catalytic layer; and pressing the catalytic layer with a conductive current collector and a gas diffusion film to obtain the electrode.
    Type: Application
    Filed: October 26, 2022
    Publication date: October 12, 2023
    Inventors: Kuang-Che Lee, Chia-Hung Li, Chien-Yao Huang, Chiun-Shian Tsai, Ting-Chuan Lee, Chiun- Rung Tsai
  • Patent number: 11778102
    Abstract: A system and method providing an accessibility tool that enhances a graphical user interface of an online meeting application is described. In one aspect, a computer-implemented method performed by an accessibility tool (128), the method includes accessing (802), in real-time, audio data of a session of an online meeting application (120), identifying (804) a target user, a speaking user, and a task based on the audio data, the speaking user indicating the task assigned to the target user in the audio data, generating (806) a message (318) that identifies the speaking user, the target user, and the task, the message (318) including textual content, and displaying (808) the message (318) in a chat pane (906) of a graphical user interface (902) of the online meeting application (120) during the session.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: October 3, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Shahil Soni, Charles Yin-Che Lee
  • Patent number: 11767077
    Abstract: A quick release structure includes a rod member, an arm member, a restriction member, and a pushing means. The rod member includes a toothed member having a plurality of rows of first teeth arranged spacedly thereon. The arm member has a plurality of rows of second teeth arranged spacedly on its inner peripheral surface. The arm member is sleeved on the toothed member and is axially slidable. The restriction member is disposed on the rod member. The pushing means is arranged between the rod member and the arm member to make the rows of first teeth and the rows of second teeth being engaged normally. When the arm member is moved axially to a rotation position, the rows of first teeth and the rows of second teeth are staggered and aligned alternately so that the arm member is rotatable relative to the rod member.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 26, 2023
    Inventor: Chung-Che Lee
  • Patent number: 11769727
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
    Type: Grant
    Filed: September 6, 2021
    Date of Patent: September 26, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Chien-Cheng Tsai, Feng-Ming Huang
  • Patent number: 11769035
    Abstract: Techniques are described automatically determining runtime configurations used to execute recurrent neural networks (RNNs) for training or inference. One such configuration involves determining whether to execute an RNN in a looped, or “rolled,” execution pattern or in a non-looped, or “unrolled,” execution pattern. Execution of an RNN using a rolled execution pattern generally consumes less memory resources than execution using an unrolled execution pattern, whereas execution of an RNN using an unrolled execution pattern typically executes faster. The configuration choice thus involves a time-memory tradeoff that can significantly affect the performance of the RNN execution. This determination is made automatically by a machine learning (ML) runtime by analyzing various factors such as, for example, a type of RNN being executed, the network structure of the RNN, characteristics of the input data to the RNN, an amount of computing resources available, and so forth.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 26, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Lai Wei, Hagay Lupesko, Anirudh Acharya, Ankit Khedia, Sandeep Krishnamurthy, Cheng-Che Lee, Kalyanee Shriram Chendke, Vandana Kannan, Roshani Nagmote
  • Patent number: 11761905
    Abstract: A semiconductor device inspection method including: depositing a dielectric material over a substrate to form an interconnect-level dielectric (ILD) layer; patterning the ILD layer to form via structures in the ILD layer; depositing an electrically conductive material to form an inspection layer on the ILD layer and in the via structures; imaging the inspection layer to generate image data; and detecting any defects in the via structures by analyzing the image data.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Che Lee, Huai-Ying Huang
  • Patent number: 11758710
    Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: September 12, 2023
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wang Jhan, Yu-Cheng Tung, Fu-Che Lee, Chien-Cheng Tsai, An-Chi Liu, Ming-Feng Kuo, Gang-Yi Lin, Junyi Zheng
  • Publication number: 20230282274
    Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a bit line connected to a plurality of memory cells of a memory array, the bit line having a first length. The memory device includes a first programmable bit line having a second length determined based on a size of the memory array, and a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is configured to transfer a charge from the bit line to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit configured to discharge a stored charge in the first programmable bit line.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Che-An Lee, Hau-Tai Shieh, Cheng Hung Lee
  • Patent number: 11749569
    Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee