Abstract: Disclosed are metal-insulator-metal capacitors and integrated chips. In one embodiment, a metal-insulator-metal capacitor includes N electrodes and (N?1) passivation layers, wherein the N electrodes and the (N?1) passivation layers are alternately stacked on a substrate. N is an integer larger than 1. Thicknesses of the N electrodes gradually increase in a direction parallel to a normal direction of the substrate.

Abstract: An electronic device performance adjustment system and an electronic device performance adjustment method are provided. The electronic device performance adjustment system includes an electronic device, a power supply, and a battery. The electronic device is configured to have multiple operation powers. The power supply is coupled to the electronic device. The power supply is configured to provide a supply current to the electronic device. The battery is coupled to the electronic device and the power supply. The battery is configured to provide a battery current to the electronic device. The power supply is configured to charge the battery. The battery has a battery level. The electronic device further includes a controller coupled to the battery. The controller is configured to determine whether to adjust the operation power of the electronic device according to a change in the battery level.

Abstract: A method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers. Performing the patterning process includes: performing a first etching process to remove a first portion of the stack structure exposed by the mask layer; performing a first trimming process on the mask layer to remove a portion of the mask layer, and a first trimmed mask layer is formed; and performing a second etching process to remove a second portion of the stack structure exposed by the first trimmed mask layer.

Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Abstract: A semiconductor structure includes a substrate comprising a peripheral region and a memory region defined thereon, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, an opening on the peripheral region of the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an interconnecting structure disposed on the second dielectric layer and two sides of the opening, a contact structure disposed in the lower portion of the opening, and a spacer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnecting structure.

Abstract: A semiconductor structure includes a substrate, a contact structure disposed on the substrate, and two first gate structures disposed on the substrate and at two sides of the first contact structure. The contact structure has a T-shaped cross-sectional profile having a first portion contacting the substrate and a second portion disposed on the first portion. A top surface of the second portion of the contact structure is flush with top surfaces of the two first gate structures.

Abstract: A fluid pressurizing structure and fan using same are disclosed. The fluid pressurizing structure includes a hub having a plate portion located therearound. The plate portion has a first and a second surface provided with a plurality of first and second hollow protrusions, respectively. Each of the first hollow protrusions has a first fluid inlet and a first fluid outlet, and each of the second hollow protrusions has a second fluid inlet and a second fluid outlet. The first and second fluid outlets extend through the plate portion to communicate the first and second fluid inlets with the second and first surface, respectively. When the fan rotates, fluid drawn thereinto sequentially flows through the first fluid inlets and outlets and the second fluid inlets and outlets in a helical movement in cycles, and is therefore continuously pressurized, which facilitates reduced fan vibration and noise and fan motor power consumption.

Abstract: A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.

Abstract: The invention provides an optical lens including a first lens, a second lens, a third lens, a fourth lens, and a fifth lens with refracting power in order from a light incidence side to a light-emitting side along an optical axis, and at least one glass lens is included. The first lens has a positive refracting power, the second lens has a positive refracting power, and the third lens has a negative refracting power. The optical lens satisfies a condition of 0.5EFL<EFLG<2EFL, where EFL is an effective focal length of the optical lens, and EFLG is an effective focal length of the at least one glass lens. The optical lens is adapted for receiving an image beam from the light incidence side, and the image beam forms a stop on the light-emitting side after passing through the optical lens. A display device is also proposed.

Abstract: The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Abstract: A centrifugal fan frame body structure includes a lower case body and a cover body. The lower case body has a bottom section and an outer wall section. The outer wall section is formed with a wind outlet. The cover body and the lower case body are correspondingly mated with each other to form a space. In the space, the lower case body and the cover body define therebetween a first height. The lower case body and the cover body define therebetween a second height at the wind outlet. The second height is larger than the first height. The height of the wind outlet is enlarged, whereby the wind outlet will not be blocked by the cooperative heat dissipation component (module) so that the flow field efficiency is enhanced and the noise is lowered.

Abstract: A head-up display device adapted to project a first image beam and a second image beam onto a target element is provided. The head-up display device includes a display unit, a first optical module, and a second optical module. The first and the second image beams from the display unit are sequentially transmitted the first and the second optical modules. The first image beam and the second image beam are respectively reflected by the second optical module out of the head-up display, and then transmitted to the target element to form a first virtual image and a second virtual image. Through the first optical module, the optical path length of the first image beam from the display unit to the position of the first virtual image is greater than the optical path length of the second image beam from the display unit to the position of the second virtual image.

Abstract: A head-up display device including a display unit, a polarization beam-splitting module, and an optical module is provided. The polarization beam-splitting module receives a first image beam and a second image beam from the display unit, and transmits the first image beam and the second image beam to the optical module. The first image beam and the second image beam are respectively reflected by the optical module to an outside of the head-up display device, and then transmitted to a target element, to form a first virtual image and a second virtual image. By the polarization beam-splitting module, an optical path length of the first image beam from the display unit to a position of the first virtual image formed by itself is longer than an optical path length of the second image beam from the display unit to a position of the second virtual image formed by itself.

Abstract: A memory array and a method for forming the memory array are disclosed. The memory array includes memory elements, selectors and conductive vias. Each selector includes two pairs of fin structures. The conductive vias are electrically coupled to the two pairs of fin structures of the selectors.

Abstract: A telescopic structure of a faucet having a movable tube contains: a body, a water supply tube, a movable tube, a spring, and a depressurization element. The body includes a screwing portion, a coupling portion, and a water outlet. The water supply includes an upright extension and an opening. The movable tube includes a slide portion and a water head engaged with the opening of the water supply tube and is pulled with the movable tube based on using requirements. The spring is accommodated in the upright extension and is fitted on the movable tube. The depressurization element includes a first face, a second face opposite to the first face, a peripheral face defined between and connected with the first face and the second face, and multiple flowing apertures defined proximate to a center of the depressurization element and communicating with the first face and the second face.

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

Abstract: Provided is a method for manufacturing a semiconductor device, including: forming a conductive layer on the first dielectric layer; forming a recess in the conductive layer; performing a first etching process to round a top corner of the recess; performing a second etching process to remove the conductive layer exposed from a bottom surface of the recess and thereby forming an opening having a rounding top corner in the conductive layer; and forming a second dielectric layer in the opening.

Abstract: A system and method providing an accessibility tool that enhances a graphical user interface of an online meeting application is described. In one aspect, a computer-implemented method performed by an accessibility tool (128), the method includes accessing (802), in real-time, audio data of a session of an online meeting application (120), identifying (804) a target user, a speaking user, and a task based on the audio data, the speaking user indicating the task assigned to the target user in the audio data, generating (806) a message (318) that identifies the speaking user, the target user, and the task, the message (318) including textual content, and displaying (808) the message (318) in a chat pane (906) of a graphical user interface (902) of the online meeting application (120) during the session.

Abstract: A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.