Patents by Inventor Chen-An Hsieh

Chen-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250134961
    Abstract: The present invention provides an oral formulation for activation of autologous stem cell, comprising a stem cell activator encapsulated into a water-in-oil-in-water (W/O/W) multiple emulsion; wherein the stem cell activator induces autologous CD34+CD45+ hematopoietic stem cells (HSCs), wherein the stem cell activator is selected from the group consisting of granulocyte colony-stimulating factor (G-CSF), stem cell factor (SCF) and combination thereof. The W/O/W multiple emulsion protects the stem cell activator from stomach acid digestion, preserving its bioactivity during transport to the bone marrow (BM) via the Peyer's patches of the intestinal lymphatic system.
    Type: Application
    Filed: October 31, 2024
    Publication date: May 1, 2025
    Applicant: Chienyu Investment Co., Ltd.
    Inventors: Chai Ching LIN, Cho Chen HSIEH, Ryan LIN
  • Publication number: 20250125845
    Abstract: A multi-beam liquid crystal antenna and a method of multi-beamforming are provided. The method includes: providing a liquid crystal modulation structure; utilizing a feeding structure to receive a feeding signal and to generate substantially an equiphase feeding electromagnetic wave to patch antenna units of the liquid crystal modulation structure; generating, by the patch antenna units, first radiation intensities and second radiation intensities respectively when the patch antenna units are utilized to receive alternating-current (AC) voltages respectively, so that the liquid crystal modulation structure forms an amplitude interference pattern; and utilizing interference of the feeding electromagnetic wave and the amplitude interference pattern to form electromagnetic beams, in which arrangement positions of the first radiation intensities and the second radiation intensities corresponding to the amplitude interference pattern change an azimuth angle and a tilt angle of each of the electromagnetic beams.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 17, 2025
    Inventors: Chun-I WU, Yi-Hsiang LAI, Yi-Chen HSIEH, Chuang-Yueh LIN, Ching-Huan LIN
  • Patent number: 12278173
    Abstract: An electronic package is provided and includes a substrate structure, an electronic element disposed on the substrate structure and an encapsulation layer encapsulating the electronic element, where at least one functional circuit is formed on a surface of a substrate body of the substrate structure, and a wire having a smaller width is arranged on a boundary line at a junction between an encapsulation area and a peripheral area, so that when a mold for forming the encapsulation layer is formed to cover the substrate structure, the mold will create a gap around the wire to serve as an exhaust passage. Therefore, when the encapsulation layer is formed, the exhaust passage can be used to exhaust air, so as to avoid problems such as the occurrence of voids or overflows of the encapsulation layer.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: April 15, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Wen-Chen Hsieh, Ya-Ting Chi, Chia-Wen Tsao, Hsin-Yin Chang, Yi-Lin Tsai, Hsiu-Fang Chien
  • Publication number: 20250081904
    Abstract: The present invention generally relates to a hydroponic culture medium and a hydroponic planting system, more particularly to a Houttuynia cordata hydroponic culture medium, a Houttuynia cordata hydroponic planting system, Houttuynia cordata extracts, a method, and applications thereof. The Houttuynia cordata hydroponic culture medium includes a plant fertilizer and a Houttuynia cordata growth-promoting additive. The Houttuynia cordata growth-promoting additive is selected from the group consisting of: vitamin B complex, seaweed essence, amino acid, microorganism, and a combination thereof. An electronic conductivity of the Houttuynia cordata hydroponic culture medium is between 0.4 ms/cm and 2.0 ms/cm.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: FANG-RONG CHANG, WEI-HUNG WU, YI-HONG TSAI, CHUNG-HSIEN CHEN, YEN-CHI LOO, HSUEH-ER CHEN, YEN-CHANG CHEN, HUI-PING HSIEH, CHEN HSIEH
  • Publication number: 20250079710
    Abstract: A liquid crystal antenna and a method of beamforming of electromagnetic waves are provided. The method includes: receiving by a feeding circuit board a feeding signal to form a feeding electromagnetic wave; applying a plurality of bias voltages respectively between a ground plane and a plurality of patch antenna units of a liquid crystal modulation structure to form an amplitude interference pattern, wherein a liquid crystal layer of the liquid crystal modulation structure is disposed between the ground plane and the patch antenna units; and utilizing interference of the feeding electromagnetic wave and the amplitude interference pattern to form an electromagnetic beam, wherein the electromagnetic beam is directed to a specific angle, and an intensity and the specific angle of the electromagnetic beam are modulated according to the variations of the feeding electromagnetic wave and the amplitude interference pattern.
    Type: Application
    Filed: December 12, 2023
    Publication date: March 6, 2025
    Inventors: Yi-Chen HSIEH, Yi-Hsiang LAI, Ching-Huan LIN
  • Publication number: 20250070769
    Abstract: A voltage selector device includes a control circuit and a selection circuit. The control circuit is configured to adjust a level of a control node according to a power enable signal, a first supply voltage, and a second supply voltage. When the first supply voltage is powered up and the second supply voltage is not powered up, the control circuit adjusts the level of the control node to a first level, and when the second supply voltage is powered up, the control circuit adjusts the level of the control node to a second level that is different from the first level. The selection circuit is configured to output, based on the level of the control node and second supply voltage, a selected one of the first supply voltage and the second supply voltage that has a higher voltage level as an output voltage.
    Type: Application
    Filed: August 20, 2024
    Publication date: February 27, 2025
    Inventors: YU-CHEN HSIEH, Tsung-Yen Tsai
  • Publication number: 20250044369
    Abstract: The invention discloses an outlier diagnosis method for a series-connected lithium battery cells, the average voltage changes at the initial stage of discharge Vx and the average voltage changes at the end of charge Vy are detected and calculated for each cell, then an outlier index and z-score are calculated, and the z-score is used to screen the cell outliers that need pay attention.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventor: Yu-Chen HSIEH
  • Publication number: 20250038097
    Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.
    Type: Application
    Filed: October 11, 2024
    Publication date: January 30, 2025
    Inventors: Chia-Wen TSAO, Wen-Chen HSIEH, Yi-Lin TSAI, Hsiu-Fang CHIEN
  • Publication number: 20250015131
    Abstract: A method includes the following steps. A transistor including a first gate structure is formed on a first substrate. A first dielectric layer is deposited over the transistor using plasma enhanced atomic layer deposition (PEALD). A multilayer stack is formed on a second substrate. The multilayer stack comprises alternately stacked semiconductor layers and sacrificial layers. A second dielectric layer is deposited over the multilayer stack using a plasma enhanced atomic layer deposition (PEALD). The second dielectric layer is bonded with the first dielectric layer. The sacrificial layers are replaced with a second gate structure.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan Chen HSIEH, Zhen-Cheng WU
  • Publication number: 20250009809
    Abstract: Disclosed herein is a method or a pharmaceutical composition for the treatment of dry eye disease or corneal wound healing, comprising administering to a subject in need thereof a therapeutically effective amount of secretome of amniotic fluid stem cells. Also provided is a use of secretome of amniotic fluid stem cells for manufacturing a medicament for the treatment of dry eye disease or corneal wound healing.
    Type: Application
    Filed: July 15, 2024
    Publication date: January 9, 2025
    Applicant: U-Neuron Biomedical Inc.
    Inventors: Shiaw-Min Hwang, Chen-An Hsieh, Pei-Cheng Lin
  • Publication number: 20240413220
    Abstract: Semiconductor structures and methods of forming the same are provided. An exemplary method includes depositing a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer over a bottom epitaxial source/drain feature formed in a bottom portion of a source/drain trench, etching back the CESL and the ILD layer to expose a top portion of the source/drain trench, performing a plasma-enhanced atomic layer deposition process (PEALD) to form an insulating layer over the source/drain trench, where the insulating layer comprises a non-uniform deposition thickness and comprises a first portion in direct contact with the ILD layer and a second portion extending along a sidewall surface of the top portion of the source/drain trench. Method also includes removing the second portion of the insulating layer and forming a top bottom epitaxial source/drain feature on the second portion of the insulating layer and in the source/drain trench.
    Type: Application
    Filed: September 27, 2023
    Publication date: December 12, 2024
    Inventors: Wan Chen Hsieh, Zhen-Cheng Wu, Tai-Jung Kuo
  • Publication number: 20240413157
    Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.
    Type: Application
    Filed: June 13, 2024
    Publication date: December 12, 2024
    Inventors: Li-Fong Lin, Wan Chen Hsieh, Chung-Ting Ko, Tai-Chun Huang
  • Patent number: 12166035
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes an isolation structure formed over a semiconductor substrate. A first fin structure and a second fin structure extend from the semiconductor substrate and protrude above the isolation structure. A first gate structure is formed across the first fin structure and a second gate structure is formed across the second fin structure. A gate isolation structure is formed between the first fin structure and the second fin structure and separates the first gate structure from the second gate structure. The gate isolation structure includes a bowl-shaped insulating layer that has a first convex sidewall surface adjacent to the first gate structure and a second convex sidewall surface adjacent to the second gate structure.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Chen Hsieh, Chung-Ting Ko, Tai-Chun Huang
  • Patent number: 12154848
    Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: November 26, 2024
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Wen Tsao, Wen-Chen Hsieh, Yi-Lin Tsai, Hsiu-Fang Chien
  • Publication number: 20240379407
    Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12119560
    Abstract: A phase shifter is provided, which includes a first substrate, a second substrate, a liquid crystal layer, a plurality of first ring-shaped electrodes and a plurality of second ring-shaped electrodes. The first substrate and the second substrate are disposed opposite to each other. The liquid crystal layer is disposed between the first substrate and the second substrate. The plurality of first ring-shaped electrodes are disposed sequentially and in interval on a side of the first substrate close to the liquid crystal layer. The plurality of second ring-shaped electrodes are disposed sequentially and in interval on a side of the second substrate close to the liquid crystal layer. A plurality of vertical projections, projected by the plurality of first ring-shaped electrodes to the second substrate, and at least partially overlapped with the plurality of second ring-shaped electrodes, respectively.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: October 15, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Shih-Yuan Chen, Hsiu-Ping Liao, Yi-Chen Hsieh, Chun-I Wu, Chuang-Yueh Lin, Yi-Hsiang Lai, Ching-Huan Lin
  • Publication number: 20240339260
    Abstract: A transformer includes a magnetic core and four windings. The magnetic core includes a first flange, a second flange and a middle core part. The first terminal of the first winding, the third terminal of the second winding, the fifth terminal of the third winding and the seventh terminal of the fourth winding are disposed on the first flange. The second terminal of the first winding, the fourth terminal of the second winding, the sixth terminal of the third winding and the eighth terminal of the fourth winding are disposed on the second flange. The first winding and the second winding are twisted with each other to dispose around the middle core part. The third winding and the fourth winding are twisted with each other to dispose around the middle core part, or the third winding and the fourth winding are disposed around the middle core part in parallel.
    Type: Application
    Filed: January 30, 2024
    Publication date: October 10, 2024
    Inventors: Yu-Chen Hsieh, Chieh-Tung Lu, Sheng-Heng Chung, Li-O Lee, Chi-Kai Lin, Chin-Hsin Lai
  • Publication number: 20240329119
    Abstract: An IC, comprising: a package; a target circuit; and a heating circuit, configured to receive a heating signal to heat at least testing portion of the target circuit to a first predetermined temperature based on the heating signal. The target circuit and the heating circuit are within the package. An IC testing method using such IC is also disclosed.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yu-Chen Hsieh, Jian-Ru Lin, Tsung-Yen Tsai, Yung-Tai Chen, Yen-Wei Liu
  • Patent number: 12062603
    Abstract: Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
  • Publication number: 20240258390
    Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh