Abstract: A system package module is provided. The system package module includes a module substrate, a plurality of first pins and a plurality of second pins. The module substrate includes a module substrate surface. The module substrate surface includes a first pin arrangement area and a second pin arrangement area. The second pin arrangement area surrounds the first pin arrangement area. The first pins are disposed in the first pin arrangement area. A first pin gap is formed between the two adjacent first pins. The second pins are disposed in the second pin arrangement area. A second pin gap is formed between the two adjacent second pins. The first pin gap is greater than the second pin gap.

Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Abstract: A ceiling fan includes a transmission unit for decoration. The transmission unit includes a base seat connected to a stator axle of a rotating motor for driving a blade module, a sun gear disposed rotatably on the base seat, a driving motor disposed on the base seat, and a first planet gear connected to the driving motor and meshing with the sun gear. The driving motor drives the first planet gear to rotate the sun gear. The sun and first planet gears are exposed at a bottom side of the base seat so as to be externally visible.

Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.

Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

Abstract: A ceiling fan includes a fan body, a sensing unit and a control unit. The fan body includes a base seat, a plurality of fan blades mounted to the base seat, and a motor mounted to the base seat for driving rotation of the fan blades about the base seat. The sensing unit includes an outer casing, a room temperature sensor, and a body temperature sensor. The control unit is mounted to the fan body, in communication with the room temperature sensor, the body temperature sensor and the motor, and operable to adjust a rotational speed of the fan blades by controlling the motor according to a room temperature and a body temperature respectively sensed by the room temperature sensor and the body temperature sensor.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a hydrophobic coating on an inner surface of an exhaust line, connecting the exhaust line to a semiconductor processing chamber, introducing a first precursor into the semiconductor processing chamber, introducing a second precursor into the semiconductor processing chamber, wherein the first precursor reacts with the second precursor to form a layer of oxide material, and pumping the first precursor and the second precursor from the semiconductor processing chamber and through the exhaust line.

Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.

Abstract: A system package module is provided. The system package module includes a module substrate, a plurality of first pins and a plurality of second pins. The module substrate includes a module substrate surface. The module substrate surface includes a first pin arrangement area and a second pin arrangement area. The second pin arrangement area surrounds the first pin arrangement area. The first pins are disposed in the first pin arrangement area. A first pin gap is formed between the two adjacent first pins. The second pins are disposed in the second pin arrangement area. A second pin gap is formed between the two adjacent second pins. The first pin gap is greater than the second pin gap.

Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.

Abstract: An antenna unit and an antenna device are provided. The antenna unit comprises a first substrate, a signal line, a first electrode, a second electrode, and an auxiliary electrode. The first substrate has a first surface and a second surface opposite to the first surface. The signal line is located on the first surface of the first substrate. The first electrode is located on the second surface of the first substrate. The first electrode is overlapped with the signal line. The first electrode is ring-shape. The second electrode has a through hole. An accommodating space of the through hole is overlapped with the first electrode. The auxiliary electrode is overlapped with the accommodating space of the through hole and the first electrode.

Abstract: An antenna device includes a first substrate, a first radiation part, a first grounding part, a second radiation part, a liquid crystal layer, and a feeding line. The first substrate includes a first surface and a second surface. The first radiation part is formed on the first surface. The first grounding part includes a slot, and the first radiation part is formed in a projection of the slot projected onto the first surface. The second radiation part is formed in the slot, and coupled with the first grounding part through a conductive segment. The liquid crystal layer is disposed between the first radiation part and the second radiation part. The feeding line is formed on the second surface, and a projection of the first radiation part projected onto the second surface is at least partially overlapping with the feeding line.

Abstract: A microwave extraction system comprises a sealed microwave box, a stirrer, a vacuum extraction tank, a vacuum machine, and an ice-water circulation unit; wherein the sealed microwave box is a tank-body set with microwave generators for accommodating the vacuum extraction tank and the stirrer, and the microwave generated by the microwave generators can penetrate into the tank-body; wherein the tank-body is set with a sealing cap to form a sealed space, and the stirrer can stir the object to be extracted; wherein the vacuum extraction tank is for placing the object to be extracted and providing the microwave penetration; wherein the ice-water circulation unit provides ice water to the tank-body; after completing the extraction operation, the ice-water circulation unit is turned-off and microwave-control to an appropriate temperature by the microwave generators; then turning-on the vacuum to perform concentration under reduced pressure; thereby improving microwave efficiency and reducing maintenance cost.

Abstract: A silicon photonic integrated system in a switch includes a multi-wavelength laser module, a first multiplexer, an optical channel, and a light signal generating element. The multi-wavelength laser module is configured to emit n laser beams with different peak wavelengths, and n is an integer greater than 2. The first multiplexer is optically coupled to the multi-wavelength laser module and configured to receive the laser beams and combine them into a combined beam. The optical channel is configured to receive a combined beam. The light signal generating element receives the combined beam through the optical channel and modulates the combined beam to emit a plurality of light output signals.

Abstract: Methods of manufacturing a conductive feature and a package are provided. One of the methods includes the following steps. A seed layer is formed. A conductive pattern is formed over the seed layer. The seed layer and the conductive pattern include a same material. A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern. A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon, wherein the step of partially removing the seed layer and the step of performing the plasma treatment process are in-situ processes.

Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.

Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.