Patents by Inventor Chen-An Hsieh

Chen-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840129
    Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
  • Patent number: 10838465
    Abstract: An electronic apparatus shell cover includes a body, a dust blocking screen, and a plurality of structural ribs. The body includes an opening and a plurality of assembling grooves. The opening penetrates through the body. The assembling grooves are on a second surface of the body and adjacent to the opening. The dust blocking screen includes a screen surface and a plurality of assembling parts. The screen surface is mounted in the opening and coplanar with a first surface of the body. The assembling parts are disposed in the assembling grooves. The structural ribs are connected to the first surface of the body and on the dust blocking screen. The dust blocking screen is coplanar with the first surface, and the internal accommodating space of the electronic apparatus shell cover is increased. Furthermore, the structural ribs can increase mechanical strength of the shell cover, can enhance heat exchange efficiency.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 17, 2020
    Assignees: MICRO-STAR INT'L CO., LIMITED., MSI ELECTRONIC (KUN SHAN) CO., LTD.
    Inventors: Chung-Bi Lee, Ming-Kan Chang, Guo-Chen Hsieh, Jia-Jun Hong
  • Publication number: 20200354155
    Abstract: An apparatus for transporting a plurality of bars having an axial direction is disclosed. The apparatus includes a storage device and a conveying device. The storage device includes an accommodating area configured to accommodate the plurality of bars side by side along a first direction substantially perpendicular to the axial direction; a first ramp having a front end and a rear end, wherein the front end is adjacent to the accommodating area and receives the plurality of bars sequentially, and the received plurality of bars roll from the front end to the rear end on the first ramp in a second direction; and a counting device adjacent to the rear end and operable to allow a predetermined quantity of the plurality of bars to exit the storage device in the second direction. The conveying device includes a receiving end, an output end and a second ramp.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 12, 2020
    Inventors: Han-Chao Chang, Wen-Tse Hsiao, Yu-Chen Hsieh
  • Patent number: 10787366
    Abstract: A method for manufacturing a graphitic sheet is used to obtain the graphitic sheet with similar characteristics to graphene. The method includes forming an octadecyltrichlorosilane (OTS) layer on a substrate to obtain a composite. The composite is annealed at 250-400° C. for 30-90 minutes, forming the graphitic sheet on the substrate via self-assembly of octadecyltrichlorosilane (OTS) in the OTS layer. The annealed composite is immersed in water, followed by being sonicated for 2 minutes with a frequency of 40 kHz and a power output of 200 W, to separate the graphitic sheet from the substrate.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: September 29, 2020
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventor: Shu-Chen Hsieh
  • Publication number: 20200285283
    Abstract: An electronic apparatus shell cover includes a body, a dust blocking screen, and a plurality of structural ribs. The body includes an opening and a plurality of assembling grooves. The opening penetrates through the body. The assembling grooves are on a second surface of the body and adjacent to the opening. The dust blocking screen includes a screen surface and a plurality of assembling parts. The screen surface is mounted in the opening and coplanar with a first surface of the body. The assembling parts are disposed in the assembling grooves. The structural ribs are connected to the first surface of the body and on the dust blocking screen. The dust blocking screen is coplanar with the first surface, and the internal accommodating space of the electronic apparatus shell cover is increased. Furthermore, the structural ribs can increase mechanical strength of the shell cover, can enhance heat exchange efficiency.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 10, 2020
    Inventors: Chung-Bi LEE, Ming-Kan CHANG, Guo-Chen HSIEH, Jia-Jun HONG
  • Publication number: 20200243973
    Abstract: An antenna unit and an antenna device are provided. The antenna unit comprises a first substrate, a signal line, a first electrode, a second electrode, and an auxiliary electrode. The first substrate has a first surface and a second surface opposite to the first surface. The signal line is located on the first surface of the first substrate. The first electrode is located on the second surface of the first substrate. The first electrode is overlapped with the signal line. The first electrode is ring-shape. The second electrode has a through hole. An accommodating space of the through hole is overlapped with the first electrode. The auxiliary electrode is overlapped with the accommodating space of the through hole and the first electrode.
    Type: Application
    Filed: July 17, 2019
    Publication date: July 30, 2020
    Applicant: Au Optronics Corporation
    Inventors: Yi-Chen Hsieh, Yi-Hsiang Lai, Ching-Huan Lin
  • Publication number: 20200243974
    Abstract: An antenna device includes a first substrate, a first radiation part, a first grounding part, a second radiation part, a liquid crystal layer, and a feeding line. The first substrate includes a first surface and a second surface. The first radiation part is formed on the first surface. The first grounding part includes a slot, and the first radiation part is formed in a projection of the slot projected onto the first surface. The second radiation part is formed in the slot, and coupled with the first grounding part through a conductive segment. The liquid crystal layer is disposed between the first radiation part and the second radiation part. The feeding line is formed on the second surface, and a projection of the first radiation part projected onto the second surface is at least partially overlapping with the feeding line.
    Type: Application
    Filed: June 19, 2019
    Publication date: July 30, 2020
    Inventors: Yi-Chen HSIEH, Yi-Hsiang LAI, Ching-Huan LIN
  • Publication number: 20200158957
    Abstract: A silicon photonic integrated system in a switch includes a multi-wavelength laser module, a first multiplexer, an optical channel, and a light signal generating element. The multi-wavelength laser module is configured to emit n laser beams with different peak wavelengths, and n is an integer greater than 2. The first multiplexer is optically coupled to the multi-wavelength laser module and configured to receive the laser beams and combine them into a combined beam. The optical channel is configured to receive a combined beam. The light signal generating element receives the combined beam through the optical channel and modulates the combined beam to emit a plurality of light output signals.
    Type: Application
    Filed: September 9, 2019
    Publication date: May 21, 2020
    Applicant: Centera Photonics Inc.
    Inventors: Chien-Chen Hsieh, Shang-Jen Yu, Hsiao-Chin Lan
  • Publication number: 20200126850
    Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
  • Publication number: 20200063181
    Abstract: A fluorescent probe is obtained via hydrolysis and condensation reaction using 3-glycidoxypropyl trimethoxysilane. The fluorescent probe includes a silicon oxide core and a self-assembled monolayer. The self-assembled monolayer has an epoxide group, and joins the silicone oxide core by a covalent bond. The epoxide group of the fluorescent probe can form a conjugated bond with a molecule with an amino group via an aminolysis reaction, forming a nanoparticle including the molecule and the fluorescent probe.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Inventors: SHU-CHEN HSIEH, PEI-YING LIN
  • Publication number: 20200051949
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20200039829
    Abstract: A method for manufacturing a graphitic sheet is used to obtain the graphitic sheet with similar characteristics to graphene. The method includes forming an ocatadecyltrichlorosilane (OTS) layer on a substrate to obtain a composite. The composite is annealed at 250-400° C. for 30-90 minutes, forming the graphitic sheet on the substrate via self-assembly of ocatadecyltrichlorosilane (OTS) in the OTS layer. The annealed composite is immersed in water, followed by being sonicated for 2 minutes with a frequency of 40 kHz and a power output of 200 W, to separate the graphitic sheet from the substrate.
    Type: Application
    Filed: September 4, 2018
    Publication date: February 6, 2020
    Inventor: Shu-Chen Hsieh
  • Publication number: 20200013750
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20200006240
    Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.
    Type: Application
    Filed: October 11, 2018
    Publication date: January 2, 2020
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai, Chen-Hua Yu
  • Patent number: 10522501
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10515848
    Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
  • Patent number: 10494556
    Abstract: A magnetic and thermally conductive material is provided, which includes a thermally conductive compound powder, and an iron-containing oxide at a surface of the thermally conductive compound powder, wherein the iron-containing oxide is an oxide of iron with an other metal, and the other metal is nickel, zinc, copper, cobalt, magnesium, manganese, yttrium, lithium, aluminum, or a combination thereof. A thermally conductive and dielectric layer is also provided, which includes a magnetic and thermally conductive material and a resin, wherein the thermally conductive material includes a thermally conductive compound powder, and an iron-containing oxide at a surface of the thermally conductive compound powder, wherein the iron-containing oxide is an oxide of iron with an other metal, and the other metal is nickel, zinc, copper, cobalt, magnesium, manganese, yttrium, lithium, aluminum, or a combination thereof.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 3, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Pin Wu, Mean-Jue Tung, Ching-Chen Hsieh, Wei-Ta Yang, Meng-Song Yin
  • Publication number: 20190326167
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 24, 2019
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20190318986
    Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.
    Type: Application
    Filed: February 1, 2019
    Publication date: October 17, 2019
    Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
  • Publication number: 20190273045
    Abstract: Methods of manufacturing a conductive feature and a package are provided. One of the methods includes the following steps. A seed layer is formed. A conductive pattern is formed over the seed layer. The seed layer and the conductive pattern include a same material. A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern. A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon, wherein the step of partially removing the seed layer and the step of performing the plasma treatment process are in-situ processes.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh