Patents by Inventor Chen-An Hsieh

Chen-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10522501
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10515848
    Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
  • Patent number: 10494556
    Abstract: A magnetic and thermally conductive material is provided, which includes a thermally conductive compound powder, and an iron-containing oxide at a surface of the thermally conductive compound powder, wherein the iron-containing oxide is an oxide of iron with an other metal, and the other metal is nickel, zinc, copper, cobalt, magnesium, manganese, yttrium, lithium, aluminum, or a combination thereof. A thermally conductive and dielectric layer is also provided, which includes a magnetic and thermally conductive material and a resin, wherein the thermally conductive material includes a thermally conductive compound powder, and an iron-containing oxide at a surface of the thermally conductive compound powder, wherein the iron-containing oxide is an oxide of iron with an other metal, and the other metal is nickel, zinc, copper, cobalt, magnesium, manganese, yttrium, lithium, aluminum, or a combination thereof.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 3, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Pin Wu, Mean-Jue Tung, Ching-Chen Hsieh, Wei-Ta Yang, Meng-Song Yin
  • Publication number: 20190326167
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 24, 2019
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20190318986
    Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.
    Type: Application
    Filed: February 1, 2019
    Publication date: October 17, 2019
    Inventors: Chen-Hua Yu, Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo
  • Publication number: 20190273045
    Abstract: Methods of manufacturing a conductive feature and a package are provided. One of the methods includes the following steps. A seed layer is formed. A conductive pattern is formed over the seed layer. The seed layer and the conductive pattern include a same material. A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern. A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon, wherein the step of partially removing the seed layer and the step of performing the plasma treatment process are in-situ processes.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
  • Patent number: 10361122
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20190214317
    Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.
    Type: Application
    Filed: January 21, 2019
    Publication date: July 11, 2019
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Yun Chen Hsieh, Hung-Jui Kuo
  • Patent number: 10335445
    Abstract: The present invention relates to phorbol esters from the seeds of Aquilaria malaccensis by a series of chromatographic processes, and compositions containing these congeners for the treatment of allergic responses.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 2, 2019
    Assignee: WE-WIN APPLIED BIO-TECH CO., LTD.
    Inventors: Fang-Rong Chang, Bing-Hung Chen, Hsue-Yin Hsu, Yang-Chang Wu, Chen Hsieh, Hui-Ping Hsieh
  • Publication number: 20190157240
    Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.
    Type: Application
    Filed: July 6, 2018
    Publication date: May 23, 2019
    Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10297551
    Abstract: A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An inter-dielectric layer is formed over a substrate. A seed layer is formed over the inter-dielectric layer. A plurality of conductive patterns are formed over the seed layer. The seed layer and the conductive patterns include a same material. While maintain a substantially uniform pitch width in the conductive pattern, the seed layer exposed by the conductive patterns is selectively removed through a dry etch process to form a plurality of seed layer patterns. The conductive patterns and the seed layer patterns form a plurality of redistribution conductive patterns.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
  • Patent number: 10206448
    Abstract: A wearable step-counting shoe includes a shoe body and a pedometer. The shoe body includes a shoe sole having opposite inner and outer sides, and a groove surface defining amounting groove. The pedometer is removably disposed in the mounting groove and includes a pedometer body having opposite first and second faces and configured to detect and record the number of steps taken by a user, and a screen disposed on the second face and configured to display the detected number of steps. An engaging unit is provided to fix the pedometer on the shoe body, and includes a first engaging portion provided on the groove surface, and a second engaging portion provided on the pedometer and releasably engageable with the first engaging portion.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: February 19, 2019
    Assignee: HOMEWAY TECHNOLOGY CO., LTD.
    Inventors: Chin-Hsing Hsieh, Tsung-Hsien Hsieh, Ming-Chia Hsieh, Tung-Chen Hsieh
  • Publication number: 20190025279
    Abstract: This disclosure is related to a testing instrument with quality control determination and a method thereof. The testing instrument includes a housing, a monitor, a scanning key, a scanning area, a strip slot and a control circuit. The test instrument has a nursing staff ID table, a strip corresponding table and a quality control testing performance table which are all embedded in the control circuit. The three tables correspond with a step of determining whether the operator matches one of the members listed on the nursing staff ID table, and a step of performing the quality control testing to achieve the automatic determination of whether or not a quality control test has been performed and whether or not the quality control test is passed.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Inventor: MING-CHEN HSIEH
  • Patent number: 10186462
    Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Yun Chen Hsieh, Hung-Jui Kou
  • Publication number: 20180327808
    Abstract: A nanodot for detecting glucose concentration includes a silicon oxide core, a self-assembled monolayer having a 3-glycidoxypropyl trimethoxysilane group, and a glucose oxidase particle. The self-assembled monolayer joins the silicon oxide core by a covalent bond, and the glucose oxidase particle joins the 3-glycidoxypropyl trimethoxysilane group of the self-assembled monolayer by a conjugated bond. Moreover, a method for detecting glucose concentration by the nanodot includes oxidizing a glucose molecule in a glucose solution by the glucose oxidase particle of the nanodot, producing a hydrogen peroxide molecule; fluorescent quenching the nanodot by the hydrogen peroxide molecule, resulting in a change in fluorescent intensity of the nanodot; and detecting the change in fluorescent intensity of the nanodot.
    Type: Application
    Filed: June 14, 2017
    Publication date: November 15, 2018
    Inventors: SHU-CHEN HSIEH, PEI-YING LIN
  • Patent number: 10105906
    Abstract: A structured light generating device and a measuring system and method are provided. The structured light generating device includes: a light modulating element for receiving a projection light beam and modulating the projection light beam into a first structured light beam having a pattern, and a light shifting element corresponding to the light modulating element for receiving and shifting the first structured light beam to generate a second structured light beam having the pattern. A shift difference is formed between the first structured light beam and the second structured light beam, and the first structured light beam and the second structured light beam are superimposed to form a superimposed structured light beam so as to improve resolution.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: October 23, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Hung Cho, Hsin-Yi Chen, Yi-Chen Hsieh, Cheng-Ta Mu
  • Patent number: 10017385
    Abstract: The present invention provides a catalyst composition for producing hydrogen and preparation method and use thereof, wherein the catalyst composition comprises a catalytic component and a supporter having a pyrochlore structure. By using the catalyst composition of the present invention, carbon deposition can be reduced and the oxidative steam reforming of ethanol could be operated for a long period of time with high ethanol conversion rate and selectivity of hydrogen.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 10, 2018
    Assignee: National Chiao Tung University
    Inventors: Chi-Shen Lee, Yuan-Chia Chang, Ho-Chen Hsieh
  • Publication number: 20180151453
    Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.
    Type: Application
    Filed: July 3, 2017
    Publication date: May 31, 2018
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Yun Chen Hsieh, Hung-Jui Kou
  • Publication number: 20180137342
    Abstract: A skin analyzer includes a base, an optical imaging system, a flash module, a circuit module, a computing module and a display module. The optical imaging system is disposed on the base for capturing an image of an imaging area. The flash module is disposed on at least one side of the optical imaging system. The circuit module is disposed in the base and electrically connected with the optical imaging system and the flash module. The computing module has a signal transmitting connection with the circuit module. The display module has a signal transmitting connection with the computing module.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Inventors: Chen-Yi HUANG, Yi-Chen HSIEH, Yu-Cheng KE, Tsung-Yung HUNG
  • Patent number: 9948868
    Abstract: A multi-point spectral system includes an imaging lens, an image capturing module and a multiwavelength filter (MWF) disposed between the imaging lens and the image capturing module. The MWF has a plurality of narrow-bandpass filter (NBPF) units arranged in an array, and each of the plurality of NBPF units has a respective predetermined central transmitted wavelength. The multi-point spectral system is provided to capture plural spectral images of a scene, which contain spectral or color information of the scene. The multi-point spectral system may utilize the information of the plural spectral images to recognize features revealed at the scene.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 17, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yan-Rung Lin, Hsin-Yi Chen, Chia-Liang Yeh, Yi-Chen Hsieh