Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: An endoscope includes a control module, a lens module, a cover, and an encapsulation. The lens module is electrically connected to the control module. The cover has a transparent area, and the cover covers the lens module in a sealing manner. The encapsulation encapsulates the cover and the control module, and exposes the transparent area, such that the encapsulation serves as a shell of the endoscope.

Abstract: An electrostatic discharge protective circuit. The electrostatic discharge protective circuit includes a gate electrode. A drain is formed at one side of the gate electrode. A source is formed at another side of the gate electrode, wherein the gate electrode, the drain and the source together form a transistor. A plurality of isolation structures penetrates through the gate electrode and respectively isolates the drain and the source into a plurality of drain regions and source regions. A plurality of contacts is respectively formed on the gate electrode, the drain regions and the source regions, wherein each drain region and each source region respectively have at least one contact.

Abstract: An electrostatic discharge protection apparatus. A drain region is formed under a pad. A gate is formed at a periphery of the pad, while a source region is formed at a periphery of the gate. Another kind of electrostatic discharge protection apparatus is also presented with a drain region formed under a pad. More than one gate is formed at a periphery of the pad, and each gate is surrounded with a source region. Further in the invention, an electrostatic discharge protection apparatus is further presented with a P-type and N-type drain region located under a pad. A first gate and a second gate are formed at a periphery of pad corresponding thereto, respectively. In the above manners, the layout of the electrostatic discharge protection can be highly packed, that is, the occupied area is greatly reduced.

Abstract: A method of fabricating a flash memory cell is described. The present invention forms the flash memory cell comprising an asymmetric source/drain region with tilt implantation. By the tilt implantation, a lightly doped region can be formed under a spacer before the formation of the spacer, or after the formation of the spacer. A photo-mask procedure thus does not need in the invention for forming the lightly doped source region. The fabrication process is simplified and the fabrication cost is also reduced.

Abstract: A method for forming a dielectric layer with a low dielectric constant (low-k) is described. A semiconductor substrate is provided. A dielectric layer is formed on the substrate. A doping step is performed on the dielectric layer. An annealing step is performed and a gas is simultaneously fed so that the dielectric layer is converted into the low-k dielectric layer.

Abstract: A method of manufacturing borderless contact can compensate for misalignment that occurs during formation of the contacts. First, a substrate with a gate structure on it is provided. The substrate also has source/drain regions. Spacers are formed on the sidewalls of the gate structure. Thereafter, an insulating layer conformal to the substrate profile is formed over the substrate. Then, a portion of the insulating layer is removed so that the remaining isolating layer at least covers the gate structure and the source/drain regions. Next, a dielectric layer having openings is formed over the insulating layer, and then a portion of the insulating layer at the bottom of the openings is removed to expose the source/drain region, thereby forming contact openings. Finally, conductive material is deposited into the contact openings to form contacts that couple electrically with the respective source/drain regions.

Abstract: An electrostatic discharge protective circuit formed on a substrate is described. A gate electrode is formed over the substrate. A drain region is formed in the substrate at one side of the gate electrode. A source region is formed in the substrate at the other side of the gate electrode. A dielectric layer having a drain contact and a source contact formed therein is formed over the substrate, wherein the drain contact is electrically coupled to the drain region and the source contact is electrically coupled to the source region. A plurality of floating polysilicons is formed on the substrate in the dielectric layer between the drain contact and the gate electrode. Since the floating polysilicons are staggered on the substrate in a checkered pattern, the electrostatic discharge transient current path is greatly increased. Therefore, the electricity dissipation length is greatly increased. Hence, the protective efficacy of the electrostatic discharge protective circuit can be improved.

Abstract: A method of manufacturing an electrostatic discharge protective circuit. A substrate having an inner circuit region and an electrostatic discharge protective circuit is provided. The inner circuit region comprises a first gate electrode, a source/drain region and a first suicide layer formed on the first gate electrode. The electrostatic discharge protective circuit region comprises a second gate electrode and a second silicide layer formed on the second gate electrode. A salicide block layer is formed to cover the electrostatic discharge protective circuit region. A salicide process is performed. The salicide block layer is removed to expose the electrostatic discharge protective circuit region.

Abstract: A three-dimensional, deep-trench, high-density ROM and its manufacturing method are provided. The ROM device comprises a silicon substrate having a plurality of parallel trenches above it surface, wherein, between every two adjacent trenches, there is a higher region. During programming of the ROM device, deeper trenches are formed to define the OFF-state non-conducting memory cells, so that misalignment problems that lead to transistor cell leakage are prevented. The ROM device provides reduced breakdown of the source/drain regions as well.

Abstract: The present invention provides an improved method of forming a dual damascene structure. Patterns of a metallic trench and a via hole are formed by using the photolithography process twice. After the first etching step of the dielectric layer the first photoresist layer is not removed. Thus, the first photoresist layer is used with the second photoresist layer as masks in the second etching step of the dielectric layer. The self-aligned method of forming a dual damascene structure thus is provided. In addition, a titanium layer or a titanium nitride layer can be formed on the dielectric layer after the first etching step of the dielectric layer and is used as an anti-reflection layer.

Abstract: A dual damascene process for forming interconnects such as contact plugs or vias. A first metal line is formed on a substrate structure. A first metal line is formed on the substrate structure. At least a stud is formed to cover a part of the first metal line. An insulation layer is formed to cover the substrate structure, the first metal line and the stud. A part of the insulation layer is removed to expose the stud. The expose stud is removed to form a contact window to expose the part of the first metal line. A metal layer is formed to fill the contact window.

Abstract: A method of forming damascene structure has a borderless via design. The method forms a first conductive line above a substrate structure, and then forms a first dielectric layer having a via opening that exposes a portion of the first conductive layer. Thereafter, a metallic plug electrically connected to the first conductive line is formed in the via opening. Next, an insulating layer and a second dielectric layer are sequentially formed over the first dielectric layer. Subsequently, the second dielectric and the insulating layer are patterned to form a trench. Then, portions of the insulating layer at the bottom of the trench are removed to form cavity regions. Finally, a second conductive line that connects electrically with the metallic plug is formed.

Abstract: A method of forming self-aligned contact comprises the steps of forming a cap layer on top of a gate structure. Then, sidewall spacers are formed on each side of the gate structure, while a self-aligned contact opening is formed above the source/drain region. Next, a polysilicon plug that couples electrically with the source/drain region is formed inside the self-aligned contact opening. A metallic material is deposited to fill the self-aligned contact opening, thereby forming a metal plug. The polysilicon plug and the metal plug together form a self-aligned contact. Alternatively, a polysilicon plug that couples electrically with the source/drain region is formed inside the self-aligned contact opening, and then a non-metallic material is deposited to fill the self-aligned contact opening thereby forming a stud. Subsequently, the stud is removed to form an opening and then a metal plug is formed in the opening. Hence, a self-aligned contact is again formed.

Abstract: A method of fabricating a static random access memory. A substrate having a gate is provided. A source/drain region is formed in the substrate beside the gate. A metal silicide layer is formed on the source/drain region and the gate region. A conductive line which is electrically coupled to the metal silicide layer on the source/drain region is formed over the substrate. A dielectric layer having a via is formed over the substrate. A portion of the conductive line is exposed by the via. A polysilicon conductive line is formed conformably to the via and the dielectric layer. The polysilicon conductive line is electrically coupled to the conductive line. An ion implantation is performed to form a poly load of the static random access memory.

Abstract: A method of fabricating a self-aligned contact forms at least a gate and a source/drain region on a substrate, wherein a cap layer is formed on top of the gate. First spacers are formed on sidewalls of the gate. Second spacers are formed to cover the first spacers and the source/drain region. A dielectric layer having an opening is formed over the substrate. A portion of the second spacers is exposed by the opening. The second spacers exposed by the opening are removed to form a concave region. The source/drain region is exposed by the concave region. A plug that can be electrically coupled to the source/drain region is formed in the opening and the concave region.

Abstract: The invention provides an ESD protection circuit, which is formed on a semiconductor substrate. There is at least one MOS transistor branches out at a place between an I/O port and an internal circuit. The MOS transistor includes a drain region, a source region, a gate oxide layer, and a gate electrode. The source and the drain regions are formed in the substrate and located on each side of the gate electrode. An insulating layer is formed over the substrate to cover the MOS transistor. A drain contact is formed in the insulating layer with a contact to the drain region of the MOS transistor so that the drain region can be coupled to the internal circuit through the drain contact. A source contact is formed in the insulating layer with a contact to the source region of the MOS transistor so that the source region can be coupled to the I/O port through the source contact. Several floating silicide blocks is located between the insulating layer and the substrate at the drain region.