Abstract: A method of making multi-level ROM devices in which the gate width controls the threshold voltage setting of each memory unit, instead of the conventional method of setting the threshold voltage through the implantation of ions into the channel region of a memory unit. The memory units include memory units having their word line polysilicon layer completely removed, which are units in an OFF state. Memory units having part of the word line polysilicon layer removed are units with a higher threshold voltage, while memory units having the word line polysilicon layer left untouched are memory units with a lower threshold voltage.

Abstract: A method of making a flash memory cell includes patterning a series of layers over a semiconductor substrate of a first conductivity type to form a gate electrode structure. A first ion implantation procedure is performed to introduce a first impurity of a second conductivity type into the semiconductor substrate and form a heavily-doped source region and a heavily-doped drain region. A second ion implantation procedure is performed at a tilt angle of 25.degree. to 45.degree., to introduce a second impurity of the second conductivity type into the semiconductor substrate and form a pair of asymmetric lightly-doped regions, with one of the asymmetric lightly-doped regions surrounding the heavily-doped source region, and the other of the asymmetric lightly-doped regions beneath the heavily-doped drain region. An insulating spacer is formed on sidewalls of the gate electrode structure.

Abstract: A test pattern simulates conductors and interconnections of conductors of a multi-layer semiconductor device that may be subject to damage from electromigration. Test pattern elements are connected in a series circuit with two connection points for applying a test current to the elements. A break in this circuit or an increase in resistance during the test signifies that electromigration has damaged the test pattern and that the operating components of the device may have manufacturing defects that make them susceptible to electromigration. Probe points can be provided for testing particular parts of the series circuit. The pattern has at least one conductive stripe or other element in each layer of the device and it has interconnecting vias between these elements through one or more intervening layers of insulation where corresponding layer-to-layer interconnections are made in the operating components of the device. On the surface of the device, diffusions form part of the circuit path.

Abstract: A three-dimensional ROM device includes a silicon substrate having plurality of parallel trenches formed in an upper surface thereof, and a plurality of raised mesa regions. Each trench has a bottom and a pair of sidewalls, and is separated from an adjacent trench by a respective mesa region. A plurality of separated, parallel source/drain regions are provided, including a first and second source/drain region located on respective opposite sides of a respective trench bottom, and a third and fourth source/drain region located on respective opposite sides of a respective raised mesa region. Each source/drain region serves as a bit line. A gate oxide layer is located on the upper surface of the silicon substrate. A plurality of sidewall oxide layers are formed on selected sidewalls and serve as channel barriers. A plurality of silicon nitride layers are formed above selected mesa regions and trench bottoms, and serve as channel barriers.

Abstract: A process for fabricating a protective shield for polysilicon loads in SRAM devices is disclosed. The protective shield enables to protect the polyloads from resistance characteristics degradation during the subsequent plasma-based processing steps in the fabrication of the memory device after the polyloads are formed. The polyloads are formed in a photolithography procedure by utilizing a photomask defining the resistive and conductive portions of the polyloads. The process comprises the steps of forming a shield silicon oxide layer over the surface of the memory device in process, including the polyloads, and forming a shield silicon nitride layer on the top of the shield silicon oxide layer. The protective shield is then formed by etching in the shield silicon oxide and nitride layers utilizing a protective photomask. The protective photomask is the same photomask utilized in the formation of the polyloads in the previous photolithography procedural step of the fabrication of the memory device.

Abstract: A process for fabricating memory cells of flash memory devices that requires lower voltages between the drain and source regions when storing or erasing data, and avoids the punch-through problem associated with conventional flash memory devices having a high device density. The process includes forming successively on the surface of the silicon substrate a tunnel oxide layer, a floating gate layer, a dielectric layer, and a control gate layer. A portion of the tunnel oxide layer is exposed and unshielded. An ion implantation procedure is then applied to the silicon substrate to form a source region and a drain region. Sidewall spacers are then formed on the sidewalls of the control gate layer, the dielectric layer, the floating gate layer, and an unexposed portion of the tunnel oxide layer.

Abstract: A multi-stage ROM device capable of storing multi-stage data and allowing high packing density for a ROM chip thus fabricated and a process for fabricating such a multi-stage ROM device. In the ROM device, the intersection between a first bit line and a word line is formed with a diode having a threshold voltage controlled at about 0.7 V, and the intersection between another bit line and word line is formed with a bipolar transistor with a threshold voltage controlled at about 3 V-5 V. The other intersections are each formed with a permanently-OFF transistor. By using these different types of memory cells, the ROM device is capable of storing multi-stage data.

Abstract: A multiple chip module for packaging integrated circuit chips. It has a module body with multiple faces and covers. One of the faces has conduction pads. Each of the other faces has a chip receiving compartment. Each compartment includes at least one chip receiving section. The bottom boundary of the chip receiving section faces the center of the module body and each chip receiving section includes a base surrounding its bottom boundary for locating and bonding one of the chips. Conduction areas are provided on the base of each of the chip receiving sections for connecting with the pad windows of one of the chips and are connected with corresponding conduction pads through a layout in the module body. The covers cover the chip receiving compartments for sealing the chips therein.

Abstract: A process for fabricating memory cells of a read-only memory (ROM) device is disclosed. First, a silicon dioxide layer and a silicon nitride layer are successively formed on the surface of a silicon substrate. These layers are patterned by etching to form a plurality of parallel barrier strips extending along a first direction on the surface of the substrate. Impurities are then implanted into the silicon substrate by using the barrier strips as masks, to form a plurality of buried bit lines in the areas between the barrier strips. Next, insulating sidewall spacers are formed on the sidewalls of the barrier strips. A metal silicide layer is then formed over the exposed surface of the buried bit lines in a self-aligned process. A thick dielectric layer is then formed overlying the barrier strips, the insulating sidewall spacers, and the metal silicide layer.

Abstract: A DRAM with a vertical channel structure is manufactured with an epitaxial silicon layer, above a silicon substrate, and is preformed with a source region. A well is formed in the epitaxial silicon layer. A trench is formed to penetrate into the source region. A first insulating layer is formed on a surface of the trench and then a gate is formed, almost completely filling up the remaining space in the trench. A drain region is formed inside the well. A storage capacitor is formed above the drain region.

Abstract: A shield structure is formed over each of the undoped or lightly doped polysilicon load devices of a 4T SRAM cell. The shield structure may be a metal such as aluminum, titanium or tungsten and serves to protect the undoped or lightly doped resistor within a polysilicon load device from charge-induced damage during ion implantation or plasma processing steps performed on the SRAM after formation of the polysilicon load device. The polysilicon load device is defined by depositing a layer of photoresist, exposing the photoresist through a master load mask, etching, and implanting into the exposed polysilicon. After the load device is formed, a dielectric layer is deposited and then a layer of conductive material is deposited. Dummy conductor structures are formed from the layer of conductive material using photolithography and the master load mask.

Abstract: A ROM device with a 3-dimensional memory cell structure that allows a high packing density of memory cells in the ROM device. The ROM device includes a silicon substrate having a plurality of parallel trenches formed thereon. These trenches define mesa regions therebetween. Source/drain regions are then formed on the trenches and the mesa regions. Sidewall spacers are formed on lateral sides of selected trenches. A gate oxide layer is then formed over the silicon substrate. Gate layers are then formed on the gate oxide layers along a direction perpendicular to the trenches. These gate layers serve as word lines. The bit lines over the trenches and the mesa regions utilize channel areas between each neighboring pair of source/drain regions in the horizontal direction to define a plurality of horizontal memory cells at intersections with the word lines. Each horizontal memory cell can be programmed by ion implantation.

Abstract: A read-only memory device having a memory array composed of memory cells formed as P-N junction diodes when programmed to be in an ON state and as blocking capacitors when remaining in an OFF state. A number of insulators are placed on the surface of a P-type substrate isolated from each other and aligned along one first defined direction. Each of a number of N-type bit lines is located on the P-type substrate between every neighboring pair of insulators. Each of a number of switch control layers is located on a corresponding one of the N-type bit lines. Each of a number of P-type word lines is located on the insulators along a direction that is substantially perpendicular to the first direction. A punch-through voltage is applied through the switch control layers at selected memory cell locations, thereby programming the memory cell at such locations to be in an ON state. All other memory cells locations keep their switch control layers intact and are thereby programmed to be in an OFF state.

Abstract: A process for fabricating memory cells of a read-only memory (ROM) device is disclosed. First, a gate oxide layer, a first polysilicon layer, and a first silicide layer are formed subsequently on the surface of a silicon substrate. The layers are patterned to form parallel strip-shaped configurations extending along a first direction on the surface of the silicon substrate. Next, impurities are implanted into the surface of the substrate in the areas between the strip-shaped configurations thereby constituting buried bit lines of the memory cells. Sidewall spacers are then formed on the sidewalls of the strip-shaped configurations. A second silicide layer is then formed over the exposed surface of the buried bit lines in a self-aligned process, thereby improving the electrical conductivity of the buried bit lines. After that, the portions of the second silicide layer and the first polysilicon layer covering the coding region of the memory cells are removed.

Abstract: A multichip module (MCM) configuration and a method of packaging semiconductor integrated circuit chips in a multilevel arrangement are described. Essentially, a novel module template is provided for packaging multi-level semiconductor chips. The module template includes at least two chambers which communicate with each other and are arranged vertically, and a plurality of parallel pins extending outward. Each chamber contains a round-shaped stage formed on the bottom of the chamber, a plurality of leadframes formed over the stage and connected to the desired pins, and a support member formed around the upper end of the chamber. The semiconductor chips to be packaged are prepared with predetermined circuits and conductive pads. One of the semiconductor chips is first adhered to the stage of the lowest exposed chamber. The conductive pads are connected to the corresponding leadframes by metal wires. Then, a covering plate is sealed on the support member of the lowest exposed chamber.

Abstract: A structure for a read-only-memory (ROM) having both bipolar and channel transistors as memory cells to achieve efficient space utilization and higher density of ROM elements. The channel transistors include bit lines and word lines, with a threshold voltage at about 0.7 V. By implanting impurities into predetermined channel regions, memory cells become conductive or non-conductive. Bipolar transistors are formed in predetermined intersections of bit lines and word lines with a threshold voltage of about 3 V to 5 V, which can be treated as conductive memory cells that conduct current under 5 V operating voltage. Intersections of bit lines and word lines without bipolar transistors formed therein can be treated as non-conductive memory cells.

Abstract: A new method of connecting three-dimensional integrated circuit chips using trench technology is described. Semiconductor device structures are provided in and on the top side of a semiconductor substrate of a first and a second three-dimensional integrated circuit chip. Deep trenches are etched into the first semiconductor substrate. A conductive material is deposited into the trenches. An insulating material is deposited over the surface of the substrate, polished and planarized. The bottom side of the first semiconductor substrate is ground, polished, and selectively etched so that the deep trenches form protrusions from the bottom surface. A passivation layer and a polyimide layer are deposited on the bottom surface of the first semiconductor substrate and etched away around the protrusions. A passivation layer and a polyimide layer are deposited over the top surface of the second semiconductor substrate.

Abstract: A process for fabricating LDD-based MOS transistors. In the process, an active region is defined by forming a field oxide layer on a substrate. Next, a first gate oxide layer and a first polysilicon layer are formed on the substrate. A lithographic process is used to etch away part of the first gate oxide layer and the first polysilicon layer to expose areas where heavily doped source/drain regions are to be formed. A second polysilicon layer is formed and then ions are implanted to form heavily doped source/drain regions. The second polysilicon layer and the first polysilicon layer are then etched away to form a gate polysilicon layer and expose part of the gate oxide layer proximate to the heavily doped drain.

Abstract: A structure is provided comprising a semiconductor substrate having a first conductivity type, a buried source region having a second opposite conductivity type, and an epitaxial layer of the second conductivity type having a lower dopant concentration than the buried source region. Field oxide regions are formed at outer edges of the epitaxial layer. A well region of first conductivity type is implanted into the central portion of the epitaxial layer to define the active area. Trenches are etched through the well region into the buried source region. A first layer of silicon oxide is grown on the surface and within the trenches. Gate electrodes are formed by depositing a layer of polysilicon and etching back to leave the polysilicon layer only within the trenches. Ions of second conductivity type are implanted into the top portion of the well region to form drain regions. A second layer of silicon oxide is deposited over the top surfaces and planarized.

Abstract: A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.