Abstract: A method of fabricating a buried contact avoids high resistance at a junction by forming a polysilicon layer in a trench. Thus, the current passage is not cut by the trench. The resistance of the trench junction is decreased.

Abstract: The invention provides an ESD protection circuit, which is formed on a semiconductor substrate. There is at least one MOS transistor branches out at a place between an I/O port and an internal circuit. The MOS transistor includes a drain region, a source region, a gate oxide layer, and a gate electrode. The source and the drain regions are formed in the substrate and located on each side of the gate electrode. An insulating layer is formed over the substrate to cover the MOS transistor. A drain contact is formed in the insulating layer with a contact to the drain region of the MOS transistor so that the drain region can be coupled to the internal circuit through the drain contact. A source contact is formed in the insulating layer with a contact to the source region of the MOS transistor so that the source region can be coupled to the I/O port through the source contact. Several floating silicide blocks is located between the insulating layer and the substrate at the drain region.

Abstract: A method of fabricating a semiconductor device for preventing an antenna effect. In the invention, there is no additional mask layer or specific process performed. Thus, the fabrication cost does not increase. In addition, extra electrons are released through a path formed in the invention during the plasma-etching step. An antenna effect thus does not occur. The reliability of the semiconductor device is increased.

Abstract: A method for manufacturing silicon substrates having gettering capability that results in a low complexity manufacturing with a corresponding reduction in the cost of production. The first embodiment of the invention involves the use of a silicon nitride layer as a mask in the etching of the silicon substrate to form the damaged layer. The second embodiment of the invention makes use of a first pad oxide layer as a mask in the etching of the silicon substrate to form the damaged layer. Hence, a single-face etching rather than double-face etching of the silicon substrate is used in the formation of the damaged layer in this invention, so there is no need for the performance of mirror processing operations before subsequent processes.

Abstract: Provided is an electrostatic discharge protection circuit according to the invention. In a drain between a gate and a contact plug which is electrically coupled to an input line, a plurality of shallow trench isolation regions are alternately formed in a shape of lattices for extending a current flow path and efficiently increasing a dissipation length. Therefore, a current caused by an electrostatic discharge can be uniformly distributed, so that the inventive electrostatic discharge protection circuit can have an enhanced protective capability.

Abstract: A method for fabricating a field device transistor includes forming a gate oxide layer of the field device transistor by performing a thermal oxidation process. By properly controlling the thickness of the gate oxide layer, the threshold voltage of the field device transistor can be suppressed in under 5 volts to provide sufficient protection for the internal circuit. The method of the invention includes forming a gate oxide layer of a field device transistor by performing a thermal oxidation process instead of a field oxide layer in order to obtain a better control on the thickness of the gate oxide layer.

Abstract: A method for manufacturing an electrostatic discharge (ESD) protective circuit. By using the method according to the invention, since the Zener diode, which has low trigger voltage and low power consumption, is formed in the electrostatic protective circuit, the protective ability of the ESD protective circuit is greatly improved as the integration is relatively high. Furthermore, it is necessary to use an extra photo mask as the ESD implantation step and the Zener breakdown implantation step are performed when the internal circuit and the ESD protective circuit are formed simultaneously, so that the cost is reduced.

Abstract: A method for forming a dual-thickness gate oxide layer starts with forming and patterning a pad oxide layer and a silicon nitride layer on a substrate. The substrate contains pre-determined regions for accommodating the internal circuit and the ESD protection circuit respectively. A field oxide layer for separating the active regions of the internal circuit and the ESD protection circuit is formed by performing an oxidation process. A thick gate oxide layer is formed on the active region of the ESD protection circuit by oxidation after the pad oxide and the silicon nitride thereover are removed. Similarly, a thin gate oxide layer is formed on the active region of the internal circuit by oxidation after the pad oxide and the silicon nitride thereover are removed. A patterned conducting layer is then formed on the substrate as gates. An implantation process is performed to form the source/drain regions within the region of the internal circuit. Next, spacers that surround the gates are formed on the substrate.

Abstract: A method of forming local interconnects uses a dual damascene process. The process comprises the steps of first providing a substrate, and then forming a first insulating layer over the substrate. Then, a pillar-shaped second insulating layer is formed over the first insulating layer. Thereafter, a first conductive layer is formed over the first insulating layer and the second insulating layer, and then a third insulating layer is formed over the first conductive layer. In the subsequent step, a portion of the third insulating layer and the first conductive layer is polished away using a chemical-mechanical polishing operation, stopping at the surface of the second insulating layer. Next, a fourth insulating layer is formed over the third insulating layer, the second insulating layer and the first conductive layer, wherein the fourth insulating layer and the second insulating layer are made from the same material.

Abstract: A field device electrostatic discharge protective circuit is described. The field device electrostatic discharge protective circuit comprises an N-type FET, an NMOS, an impedance device and a resistor. The gate and the drain of the N-type FET connect to the input port. The drain of the NMOS connects to the internal circuit. The source of the NMOS connects to ground. The gate of the NMOS connects to the source of the N-type FET. The impedance device is set between the source of the N-type FET and the ground. The resistor is set between the drain of the N-type FET and the drain of the NMOS.

Abstract: A method for manufacturing a dual damascene structure comprises the following steps. First, a first insulator having a first trench and a second trench therein is formed on a substrate. A first conductive line and a second conductive line are formed in the first trench and the second trench, respectively. A shielding layer is formed on the first conductive line. The upper part of the second conductive line is removed to form a third trench in the first insulator. The shielding layer is removed. A second insulator is formed on the first insulator and thoroughly fills the third trench. Part of the second insulator is removed until the first conductive line is exposed. A dielectric layer is formed on the second insulator and the first conductive line. The dielectric layer is patterned to form a fourth trench and to expose the first conductive line. Finally, a third conductive line is formed in the fourth trench to electrically connect the first conductive line.

Abstract: A method for fabricating an electrostatic discharge (ESD) protection circuit on a substrate is provided. The substrate includes an internal circuit region and an ESD protection region. A first MOS transistor is formed at the internal circuit region including a first gate structure, a first spacer, a first source/drain region with a first lightly doped drain (LDD) structure. A second MOS transistor is formed at the ESD protection circuit region including a second gate structure, a second spacer, a second source/drain region with a second LDD structure. The method includes forming a conformal metal layer over the substrate. A patterned photoresist layer is formed on the metal layer to expose a portion of the metal layer. Under the exposed portion of the metal layer it includes the second spacer and a portion of the second source/drain region.

Abstract: A damascene manufacturing process capable of forming borderless via. The process includes the steps of forming a first trench in a first dielectric layer above a substrate, and then forming a conductive line within the first trench. Thereafter, a portion of the conductive line is removed to form a second trench within the first dielectric layer directly above the conductive line. Next, material is deposited into the second trench to form a cap layer. Subsequently, a second dielectric layer is deposited over the first dielectric layer, and then the second dielectric layer is patterned to form a via opening that exposes the cap layer. Next, the cap layer is removed to form a cavity region that exposes the conductive line. Finally, a plug is formed within the cavity region and the via opening such that the plug is electrically connected with the conductive line.

Abstract: A transistor structure for an ESD protection device, which includes a gate structure constituted by a connecting part and a plurality of protecting parts on a substrate. The protecting parts include a first protecting part and a second protecting part, wherein the first protecting part is located closer to the middle of the gate structure and the second protecting part is located further from the middle of the gate structure. The width of the second protecting part is larger than that of the first protecting part. There are sources and drains alternated with the protecting parts, wherein the sources include a first isolated from the drain by the first protecting part and a second source isolated from the drain by the second protecting part. The substrate junction is connected to the second source with a butting face and a butting contact is located above the butting face to connect the second source and the substrate junction simultaneously.

Abstract: A method of manufacturing interconnects disclosed in the invention comprises the following steps. First, a substrate having an insulator formed thereon is provided. A first dielectric layer having a first conductive section and a second conductive section formed therein, is formed on the insulator. A second dielectric layer is formed over the substrate and covers the first conductive line and the second conductive line. A via hole is formed in the second dielectric layer to expose parts of the first conductive section and the second conductive section and the part of the first dielectric layer therebetween. The part of the first dielectric layer between the first conductive line and the second conductive line is removed until the insulator is exposed, thereby forming a coupling hole. And, a plug is formed in the via hole and the coupling hole, wherein the plug is electrically coupled to the first conductive section and the second conductive section.

Abstract: An improved method for fabricating an ESD protection device so as to avoid ESD damage to a wafer. The improved method includes simultaneously forming an internal circuit and the ESD protection device without additional photomask or other process. The improved method uses a P.sup.+ doped region to take the place of an N.sup.- doped region of an interchangeable source/drain region with a LDD structure for the ESD protection device, of which its trigger voltage is adjusted by simply varying the P.sup.+ concentration.

Abstract: A method of manufacturing the buried contact window of an SRAM cell. The method includes the steps of first providing a first conductive type substrate that has an isolating structure and a gate thereon. The gate comprises a gate oxide layer, a polysilicon layer and a sacrificial layer. Next, a heavily doped region of a second conductive type is formed in the substrate between the device isolating structure and the gate terminal. The heavily doped region acts as a buried contact window. Thereafter, a metal silicide layer is formed over the heavily doped region so that the two are electrically coupled. Next, the sacrificial layer is removed, and then a conductive layer that includes a polysilicon layer and a tungsten silicide layer is formed over the substrate. Subsequently, the conductive layer is patterned to form a conductive line layer and a gate stack.

Abstract: A structure of manufacturing an electrostatic discharge protective circuit for SRAM. In the structure, a MOS transistor is coupled between an input port and an internal circuit, and an input bonding pad is coupled to the input port and the internal circuit. Furthermore, the source of the MOS transistor is connected to the gate of the MOS transistor by a polysilicon layer which is coupled to a potential line. A via connects the drain of the MOS transistor to a metal layer. Then, the metal layer is coupled to the input bonding pad.

Abstract: A three-dimensional, deep-trench, high-density ROM and its manufacturing method are provided. The ROM device comprises a silicon substrate having a plurality of parallel trenches above it surface, wherein, between every two adjacent trenches, there is a higher region. During programming of the ROM device, deeper trenches are formed to define the OFF-state non-conducting memory cells, so that misalignment problems that lead to transistor cell leakage are prevented. The ROM device provides reduced breakdown of the source/drain regions as well.

Abstract: A high density transistor component and its manufacturing method which includes the steps of forming a pad oxide layer above a silicon substrate, forming a dielectric layer above the pad oxide layer, and growing an epitaxial silicon layer above the pad oxide layer covering the pad oxide layer as well as the dielectric layer. Source/drain regions including the heavily doped source/drain and the lightly doped source/drain are formed in the epitaxial silicon layer, and a gate terminal region composed from an assembly of a gate oxide layer, a gate terminal and two spacers is formed above the epitaxial silicon layer. The channel is located in the spatial location between the dielectric layer, the gate region and the source/drain regions.