Abstract: A method of performing trench isolation in a CMOS transistor, that produces no latch-up and results in an effective isolating structure without using an epitaxial growth process. A field oxide layer is provided on a silicon substrate to isolate an active region. A first conductivity-type well is formed at a predetermined position of the active region. A gate oxide layer, a polysilicon layer and a silicide layer are deposited in sequence. A first gate electrode and a second gate electrode are formed by lithography and etching techniques wherein the first gate electrode is on the well, and the second gate electrode is on the active region outside the well. A silicon nitride layer is deposited and etched back to form spacers on the side walls of the electrodes whereby slits are left between the field oxide layer and the spacers and between adjacent spacers. Trenches are formed by etching the silicon substrate in the slits.

Abstract: Disclosed is a process for fabricating a semiconductor device having both a functional region and an electrostatic discharge (ESD) protective region formed on the same substrate. A gate oxide layer is formed on both the functional region and the ESD protective region and a polysilicon layer is formed on the gate oxide layer. A mask is used to etch the polysilicon layer and the gate oxide layer to form gate electrode and also expose part of the silicon substrate. Ions are implanted to form a lightly doped source/drain electrode. An ESD mask is used to selectively remove part of the oxide layer on the functional region, thus forming an isolator on lateral sides of the gate electrode in the functional region. Ions are then implanted to form a heavily doped region and lightly doped source/drain electrode. After that, a metallization layer is formed by sputtering deposition and then rapid thermal annealing and etching are performed to form self-aligning TiSi.sub.

Abstract: A process for fabricating a MOS device having a recessed gate on a silicon substrate. Source/drain regions are formed by implanting impurities of a first conductivity type into a silicon substrate. A trench is formed in the silicon substrate, the trench being separated from the source/drain regions by side wall spacers on side walls of the trench. The source/drain regions extend to areas underlying the sidewall spacers. An anti-punchthrough region is formed by implanting impurities of a second conductivity type into a portion of the silicon substrate underlying the trench. A gate layer is formed within the trench, the gate layer being separated from the anti-punchthrough region by a gate oxide layer.

Abstract: A process for fabricating the memory cells of a read-only memory (ROM) device is disclosed. First, source and drain regions which constitute the bit-lines are formed on a silicon substrate by an ion implanting process. Thereby, channel regions are formed between the abutting bit-lines. Next, portions of the channel regions designated for coding are etched to form trenches. An insulating layer is then formed to fill the trenches. After that, a gate oxide layer is formed on the channel regions. Gate electrodes extending along a direction orthogonal to that of the bit-lines are formed on the substrate to constitute the word-lines. Therefore, the intersecting region of one word-line with two abutting bit-lines constitutes a memory cell of the ROM device. When applying a normal operating voltage, memory cells without the trenches are in an ON state and memory cells with the trenches are in an OFF state since the channel regions are blocked by the insulating layer within the trenches.

Abstract: A method of manufacturing a T-gate LDD pocket device is shown. Field oxide regions are formed in and on the surface of a semiconductor substrate. The T-gate device will be formed between the field oxide regions. A gate oxide layer is formed on the surface of the substrate between the field oxide. A layer of polysilicon is deposited over the gate oxide layer. Portions of the polysilicon layer are etched away leaving the polysilicon layer only between and over the inner edges of the field oxide. The remaining polysilicon is covered with a photoresist mask wherein the inner edges of the field oxide underlying the polysilicon are protected by the mask. The field oxide not covered by the mask are etched away to form the T-gate. A first set of ions of a first conductivity are implanted at a tilt angle to form lightly doped regions from regions where the field oxide have been removed and underlying the inner edges of the remaining field oxide.

Abstract: A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.

Abstract: A method for forming MOSFET devices, with reduced exposure to source and drain leakage currents due to punchthrough phenomena, has been developed. The structure is fabricated using a buried insulator sidewall to isolate the source and drain regions. This in turn is accomplished by creating a trench in the substrate, between the source and drain regions, and forming an insulator sidewall on the sides of the trench. A selective epitaxial process is used to refill the trench and a gate oxide is grown from the epitaxial silicon. Conventional processing completes this buried insulator MOSFET structure.

Abstract: A programmable read-only memory (PROM) and a method of fabrication are described. A plurality of bit-lines of a first conductivity type are formed in a semiconductor substrate and are spaced apart along a first direction. A dielectric layer is disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of vias at predetermined positions above the bit-lines. A plurality of word-lines of a second conductivity type are disposed on the dielectric layer and spaced apart along a second direction substantially orthogonal to the first direction. A control layer is disposed within the vias and sandwiched between the bit-lines and the word-lines, wherein each crossing region of the bit-lines and the word-lines with the control layer disposed there between define a memory cell of the programmable read-only memory.

Abstract: The present invention provides a novel MOS transistor structure and method of fabrication. To make this device, a gate electrode is formed on a silicon substrate first and a pair of shallow trenches with a depth of between 200.ANG. to 500.ANG. are formed apart on portions of the silicon substrate adjacent to the gate electrode. Next, lightly doped source/drain regions that extends to areas under the gate electrode are formed on the silicon substrate by using the large-angle-tilt implanted drain technique. The highest electric field of the lightly doped source/drain regions can be shifted into areas under the gate oxide layer at a depth of between 200.ANG. to 500.ANG.. Therefore, the probability of hot electron injection into the gate oxide layer is reduced and the device reliability is improved. In addition, the gate to drain capacitance is reduced, leading to an increase in device speed.

Abstract: A method for manufacturing electrostatic discharge (ESD) devices on a silicon substrate. The method is consistent with fabricating an integrated circuit having a buried contact structure. By modifying photolithographic masks, the ESD device and the buried contact are formed on the silicon substrate at the same time. Without any extra processing steps, the manufacturing of the ESD device is simplified thus reducing the manufacturing cost.

Abstract: A method for fabricating a MOS transistor includes forming an oxide layer over a silicon substrate of a first conductivity type. A gate electrode is formed over the oxide layer. Ions of a second conductivity type are implanted into the silicon substrate to form lightly-doped source/drain regions. Impurity-containing spacers are formed on sidewalls of the oxide layer and the gate electrode. The spacers are thermally processed to drive impurities of a first conductivity type into the source/drain regions. Finally, ions of a second conductivity type are implanted into the substrate to form heavily-doped source/drain regions.

Abstract: The structural configuration of an improved submicron metal-oxide semiconductor field-effect transistor and the method of its fabrication are disclosed. A field oxidation procedure is employed to increase the thickness of the gate oxide layer at both of its ends. The result is decreased gate and drain overlapping region parasitic capacitance, as well as decreased gate-induced drain-leakage current, due to the reduction of the electric field intensity in the overlapping region at which the thickness is increased. The resulting metal-oxide semiconductor field-effect transistor, therefore, is provided with improved operating characteristics for use at high frequencies.

Abstract: A process for fabricating MOSFET devices with a recessed lightly doped drain, (LDD), has been developed. This process initially involves conventional techniques of forming a silicided polysilicon, (polycide), gate structure, isolated from the silicided source and drain regions by a spacer sidewall insulator. The novel aspect of this process consists of removing the spacer insulator and etching a trench in the region between the metal silicided source/drain and the polycide gate structure. An angled ion implant is then performed to form lightly doped drain regions in the trench region, also extending under the polycide gate. This results in a narrowing of the channel length, thus enhancing device performance.

Abstract: A multichip array package for IC devices with a master semiconductor device supporting and electrically interconnected with a stacked array of subordinate devices. The interconnection structure has a peripheral row of contact pads on the master device. The subordinate devices each have a peripheral row of contact pads that corresponds to the peripheral row on the master device. Openings are provided through the contact pads on the subordinate devices that are in registry. The holes are filled with metal which interconnects the subordinate devices with the master device.

Abstract: A method of fabricating read only memory, (ROM), devices has been developed. This process is accomplished using self-alignment of buried N+ bit lines. Thick field oxides are used for isolation purposes. The programmable cell is obtained by growing a gate oxide in a region in which the thick field oxide has been removed. The non-programmable cells contain thick gate oxides. Polysilicon gate structures are processed to function as the word lines.

Abstract: A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysilicon sidewall spacers. A gate oxide layer is formed on the bottom of the trench by oxidation. A polysilicon gate layer is formed filling the trench. Impurities are implanted into the silicon substrate to simultaneously form heavily doped source/drain areas in spaced apart portions of the silicon substrate adjacent to the polysilicon sidewall spacers, improve the conductivity of the polysilicon gate layer, and form lightly doped source/drain areas in spaced apart portions of the silicon substrate under the silicon dioxide sidewall spacers.

Abstract: A method of fabricating MOS device with anti-punchthrough region is described. The area of anti-punchthrough region is reduced by using the control of double spacers. Moreover, this method utilizes the buried contact structure to connect to the source/drain regions, which not only reduces the contact resistance but also reduces the device size since the metal contact can be provided over the field oxide layer instead of the source/drain regions. Hence, this method is capable of fabricating submicron devices for semiconductor integrated circuit.

Abstract: A delamination test chip comprises a semiconductor substrate and a plurality of layers stacked on the substrate. The delamination test chip is included in a die with one or more other chips. The die is packaged and subjected to environmental stress. The test chip includes an arrangement of conducting films and vias which enable the detection of a delamination and enable the identification of the particular layer at which the delamination occurs.

Abstract: A new method of manufacturing a vertical channel device integrated circuit is described. A structure is provided comprising a semiconductor substrate having a first conductivity type, a buried source region having a second opposite conductivity type, and an epitaxial layer of the second conductivity type having a lower dopant concentration than the buried source region. Field oxide regions are formed at outer edges of the epitaxial layer. A well region of first conductivity type is implanted into the central portion of the epitaxial layer to define the active area. Trenches are etched through the well region into the buried source region. A first layer of silicon oxide is grown on the surface and within the trenches. Gate electrodes are formed by depositing a layer of polysilicon and etching back to leave the polysilicon layer only within the trenches. Ions of second conductivity type are implanted into the top portion of the well region to form drain regions.

Abstract: A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysilicon sidewall spacers. A gate oxide layer is formed on the bottom of the trench by oxidation. A polysilicon gate layer is formed filling the trench. Impurities are implanted into the silicon substrate to simultaneously form heavily doped source/drain areas in spaced apart portions of the silicon substrate adjacent to the polysilicon sidewall spacers to improve the conductivity of the polysilicon gate layer, and form lightly doped source/drain areas in spaced apart portions of the silicon substrate under the silicon dioxide sidewall spacers.