Abstract: A DRAM capacitor structure and its manufacturing include covering a semiconductor substrate with a first conducting layer. A first insulating layer and a second insulating layer are alternately stacked at least once above the first conducting layer to form a multi-layered structure. A contact window opening is formed in the multi-layered structure to expose a source/drain region located above the semiconductor substrate. A pattern is etch-defined on the multi-layered structure, using the first insulating layer as an etching stop layer. Part of the second insulating layer is etched away to form a cross-sectional profile similar to twin towers, with each tower having the form of a vertical T-stack. A second conducting layer covers the multi-layered structure. The first insulating layer and the second insulating layer of the multi-layered structure, as well as the second conducting layer in a top part of the multi-layered structure, are etched away to form a lower electrode.

Abstract: An electrostatic protection component and a method for forming the same. The method includes forming a gate consisting of a gate oxide layer and a conducting layer above a semiconductor substrate. Spacers are formed on the peripheral sidewalls of the gate. First heavily doped regions are formed in the semiconductor substrate. A metallic layer is formed covering the semiconductor substrate followed by a heating process. First metal silicide layers are formed above the gate while second metal silicide layers are formed above the first heavily doped regions. A photoresist layer is coated above the semiconductor substrate, exposing the first metal silicide layer and part of the second metal silicide layer adjacent to each side of the gate.

Abstract: A DRAM capacitor and a method of making the same includes the provisions of providing a semiconductor substrate having a MOS transistor with a gate and source/drain regions formed thereabove. A first insulating layer covers the semiconductor substrate. A conducting plug is formed in the first insulating layer. Thereafter, a multi-layered structure is formed above the first insulating layer and the conducting plug, with at least one pair of alternately formed layers, including a first conducting layer followed by a second insulating layer. Then, an opening is formed through the multi-layered structure to expose the conducting plug. Subsequently, a pattern is etch-defined on the multi-layered structure to expose part of the first insulating layer. After that, part of the second insulating layer is etched away, to shape the multi-layered structure into a cross-sectional profile similar to two towers, each in the form of a vertical stack of Ts, with each tower standing side-by-side and adjacent to each other.

Abstract: A high density transistor component and its manufacturing method which includes the steps of forming a pad oxide layer above a silicon substrate, forming a dielectric layer above the pad oxide layer, and growing an epitaxial silicon layer above the pad oxide layer covering the pad oxide layer as well as the dielectric layer. Source/drain regions including the heavily doped source/drain and the lightly doped source/drain are formed in the epitaxial silicon layer, and a gate terminal region composed from an assembly of a gate oxide layer, a gate terminal and two spacers is formed above the epitaxial silicon layer. The channel is located in the spatial location between the dielectric layer, the gate region and the source/drain regions.

Abstract: A method for fabricating a protection circuit for electrostatic-discharge (ESD) with an improved field device transistor includes connecting the source of the improved transistor to a ground voltage source, and connecting both the gate and the drain of the improved transistor to an I/O port and an internal circuit, which is to be protected from ESD problems. The method includes forming a gate region on a semiconductor substrate. A spacer is formed on one side of the gate region. An ion implantation process is performed to partially dope the gate region. A field oxide layer serving as a gate oxide layer is formed on the substrate within the gate region. After remove the spacer, a source region and a drain region are formed in the substrate by ion implantation. A dielectric layer is formed over the substrate with one source contact opening to expose the source region and one drain contact opening to expose the drain region. A metal layer is formed over the substrate but is separated into two parts.

Abstract: A method of forming an electrostatic discharge protection device having increased electrostatic discharge responsiveness in lightly-doped source-drain areas and a silicide layer, wherein the silicide layer is not etched so to prevent defects in the lightly-doped source-drain areas.

Abstract: A method of making a read only memory device includes forming a gate oxide layer and a silicon nitride layer in sequence above a silicon substrate. The gate oxide layer and the silicon nitride layer are etched to define a plurality of parallel strips extending in a first direction. Ions are implanted, using the parallel strips as masks, into the silicon substrate to form a plurality of buried bit lines extending in the first direction. A sidewall spacer is formed on respective sidewalls of the parallel strips. A silicide layer is formed over an exposed surface of the respective bit lines. An insulating layer is formed to cover any exposed surfaces, and fill a space located between adjacent parallel strips and above the bit lines. A portion of the insulating layer is removed to expose the silicon nitride layer and form a planar surface. The silicon nitride layer is patterned to form a plurality of coding areas. A polysilicon layer is formed to cover the coding areas as well as any other exposed surfaces.

Abstract: An electrostatic protection component and a method for forming the same. The method includes forming a gate consisting of a gate oxide layer and a conducting layer above a semiconductor substrate. Spacers are formed on the peripheral sidewalls of the gate. First heavily doped regions are formed in the semiconductor substrate. A metallic layer is formed covering the semiconductor substrate followed by a heating process. First metal silicide layers are formed above the gate while second metal silicide layers are formed above the first heavily doped regions. A photoresist layer is coated above the semiconductor substrate, exposing the first metal silicide layer and part of the second metal silicide layer adjacent to each side of the gate.

Abstract: A method for forming metal plugs using fewer masks and photolithographic processes than a conventional one and therefore able to simplify the overall manufacturing processes and reduce cost. The steps are:providing a substrate having a polysilicon gate, a source/drain region and a spacer formed on the sidewall of the polysilicon gate;forming a self-aligned metal silicide layer above the substrate and covering the polysilicon gate as well as the surface of the source/drain region;forming a first dielectric layer above the substrate, and then a first conducting layer above the first dielectric layer;using a photolithographic process to define a pattern on the first conducting layer and then etching the first dielectric layer to a certain depth;forming a second dielectric layer above the substrate;etching the first dielectric layer and the second dielectric layer until the metal silicide layer is exposed so as to form contact windows in designated regions; andforming metal plugs inside the contact windows.

Abstract: A DRAM capacitor structure and its manufacturing method which includes providing a semiconductor substrate with a MOS transistor already formed above, and that the MOS transistor includes a gate and source/drain regions, then forming a first insulating layer covering the semiconductor substrate, next forming a multi-layered structure with at least one pair of alternately formed second insulating layer followed by a third insulating layer above the first insulating layer, subsequently forming an opening through the multi-layered structure and the first insulating layer exposing the source/drain region below, thereafter etching and defining a pattern on the multi-layered structure so as to expose part of the first insulating layer, this is followed by etching the second insulating layer and forming a plurality of trenches in a horizontal direction on the sidewalls of the multi-layered structure, and then forming a lower electrode layer covering the surfaces of the multi-layered structure as well as the exposed

Abstract: A method of forming a stacked capacitor of a DRAM. A number of doped polysilicon layers and a number of tungsten silicide layers are alternately formed. The doped polysilicon layers and the tungsten silicide layers are then patterned to form a lower electrode of the stacked capacitor. The doped polysilicon layers and the tungsten silicide layers are selectively etched to form a number of lateral trenches at the sidewall of the lower electrode so that the surface area of the lower electrode is increased. A dielectric layer is formed over the exposed surface of the doped polysilicon layers and the tungsten silicide layers. A conductive layer is formed on the dielectric layer as an upper electrode of the stacked capacitor so that the stacked capacitor is completed.

Abstract: A DRAM capacitor structure and its manufacturing include covering a semiconductor substrate with a first conducting layer. A first insulating layer and a second insulating layer are alternately stacked at least once above the first conducting layer to form a multi-layered structure. A contact window opening is formed in the multi-layered structure to expose a source/drain region located above the semiconductor substrate. A pattern is etch-defined on the multi-layered structure, using the first insulating layer as an etching stop layer. Part of the second insulating layer is etched away to form a cross-sectional profile similar to twin towers, with each tower having the form of a vertical T-stack. A second conducting layer covers the multi-layered structure. The first insulating layer and the second insulating layer of the multi-layered structure, as well as the second conducting layer in a top part of the multi-layered structure, are etched away to form a lower electrode.

Abstract: A multilayer wiring structure consists of a substrate with a first set of wiring lines formed thereon. A first insulating layer covers the first set of wiring lines, a second insulating layer covers the first set of wiring lines and then a second set of wiring lines are formed on the second insulating layer. Vias are formed through the second insulating layer, the second wiring lines and the first insulating layer extending down to the surface or near the surface of the first wiring lines. Metallizations fill the vias to form connections and interconnections to and between the first wiring lines, the second wiring lines and the surface of the semiconductor device. Additional wiring lines may be formed on the surface of the second insulating layer and in contact with the metallizations.

Abstract: A structure and manufacturing method for DRAM capacitors includes providing a semiconductor substrate with a MOS transistor having a gate and source/drain regions formed thereon. A first insulating layer covers the semiconductor substrate. A multi-layered stack, with at least one pair of an alternately deposited second insulating layer followed by a third insulating layer, is formed above the first insulating layer. An opening is formed through the multi-layered structure and the first insulating layer exposing the source/drain region. Then, a plurality of trenches are formed on the sidewalls of the opening. A second conducting layer is formed over the exposed surfaces of the aforementioned layers. A pattern is defined on the second conducting layer so as to form a lower electrode structure. A dielectric layer is formed over the lower electrode layer. A third conducting layer is formed over the dielectric layer, and a pattern is defined on the third conducting layer to form the upper electrode structure.

Abstract: A low voltage electro-static discharge protective device includes a field oxide layer on a substrate, source/drain regions beside the field oxide layer in the substrate, and a threshold voltage adjustment region under the field oxide layer. The fabricating of the protective device includes forming a pad oxide layer and a silicon nitride layer on a substrate, etching the silicon nitride layer to form an opening, forming a oxide spacer on the exposed portion of the pad oxide layer around the periphery of the opening, implanting ions into the substrate, forming a field oxide layer in the opening, so that the certain type of ions form a threshold voltage adjustment region under the field oxide layer, removing the silicon nitride layer, removing the exposed pad oxide layer, and forming source/drain regions beside the field oxide layer.

Abstract: A three-dimensional ROM device includes a silicon substrate having plurality of parallel trenches formed in an upper surface thereof, and a plurality of raised mesa regions. Each trench has a bottom and a pair of sidewalls, and is separated from an adjacent trench by a respective mesa region. A plurality of separated, parallel source/drain regions are provided, including a first and second source/drain region located on respective opposite sides of a respective trench bottom, and a third and fourth source/drain region located on respective opposite sides of a respective raised mesa region. Each source/drain region serves as a bit line. A gate oxide layer is located on the upper surface of the silicon substrate. A plurality of sidewall oxide layers are formed on selected sidewalls and serve as channel barriers. A plurality of silicon nitride layers are formed above selected mesa regions and trench bottoms, and serve as channel barriers.

Abstract: A method of fabricating a bonding pad window, includes providing a substrate, which is metallized with a first metallization layer; forming a dielectric layer over the first metallization layer; defining the dielectric layer with a first mask to form a via; forming a plug in the via; forming a second metallization layer over the plug and the dielectric layer; patterning the second metallization layer to expose the dielectric layer; forming a passivation layer over the second metallization layer; and defining the passivation layer with the first mask to form the bonding pad window. This improves and simplifies the formation of a bonding pad window. For example, the process of forming a mask, which is used to form the bonding pad window, can be omitted. The previous via mask is used to form the bonding pad window and the internal circuit probing window at the same time.

Abstract: A high density mask ROM with recess channels is fabricated on a substrate by forming the bit lines through a number of field oxide layers having a bird's beak structure. In particular, every adjacent two bird's beaks of the field oxide layer are closely disposed or connected. The field oxide layers are used as masks for implanting ions to form the bit lines. Word lines are then formed over the substrate. The bird's beak mask results in the word lines having a wave shape. The resulting construction also has recessed channels between adjacent bit lines.

Abstract: A low voltage electro-static discharge protective device includes a field oxide layer on a substrate, source/drain regions beside the field oxide layer in the substrate, and a threshold voltage adjustment region under the field oxide layer. The fabricating of the protective device includes forming a pad oxide layer and a silicon nitride layer on a substrate, etching the silicon nitride layer to form an opening, forming a oxide spacer on the exposed portion of the pad oxide layer around the periphery of the opening, implanting ions into the substrate, forming a field oxide layer in the opening so that the certain type of ions form a threshold voltage adjustment region under the field oxide layer, removing the silicon nitride layer, removing the exposed pad oxide layer, and forming source/drain regions beside the field oxide layer.

Abstract: A process for fabricating MOSFET devices with a recessed lightly doped drain, (LDD), has been developed. This process initially involves conventional techniques of forming a silicided polysilicon, (polycide), gate structure, isolated from the silicided source and drain regions by a spacer sidewall insulator. The novel aspect of this process consists of removing the spacer insulator and etching a trench in the region between the metal silicided source/drain and the polycide gate structure. An angled ion implant is then performed to form lightly doped drain regions in the trench region, also extending under the polycide gate. This results in a narrowing of the channel length, thus enhancing device performance.