Abstract: A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysilicon sidewall spacers. A gate oxide layer is formed on the bottom of the trench by oxidation. A polysilicon gate layer is formed filling the trench. Impurities are implanted into the silicon substrate to simultaneously form heavily doped source/drain areas in spaced apart portions of the silicon substrate adjacent to the polysilicon sidewall spacers to improve the conductivity of the polysilicon gate layer, and form lightly doped source/drain areas in spaced apart portions of the silicon substrate under the silicon dioxide sidewall spacers.

Abstract: A MOS transistor with concave channel and method of fabrication is provided. First, a LOCOS procedure is performed to form a field oxide layer on a silicon substrate by using a barrier layer as a mask. Next, the field oxide is removed to leave a concave area in the silicon substrate. Silicon dioxide sidewall spacers are formed apart on side walls of the barrier layer. A gate oxide layer is formed on the bottom of the concave area. A polysilicon layer is formed in conformity with the exposed surfaces of the barrier layer, the silicon dioxide sidewall spacers, and the gate oxide layer. A mask layer is formed overlying the polysilicon layer within the concave area. Then, portions of the polysilicon layer not covered by the mask layer are removed, so that the remained portion of the polysilicon layer and the gate oxide layer together construct a gate electrode, while the area under the gate electrode forms a concave channel. The mask layer and the barrier layer are removed respectively.

Abstract: A method is described for testing the reliability of terminals in a semiconductor package proposes the placing of a test chip in the package, wherein the test chip has an insulating substrate, a conductive metal blanket layer on the substrate, a passivating layer over the metal layer provided with a plurality of openings, a plurality of Gold (Au) terminals in the openings bonded to the metal layer, and a master ground terminal bonded to the metal layer. Input/Output (I/O) terminals are provided in the package structure for each of the Au terminals, and master terminals are connected to the I/O terminals with wire, the test chip is sealed in the package. The resistance of each of the terminals is then monitored over a period of time to determine any change of electrical resistance, which is indicative of terminal deterioration.

Abstract: A process for fabricating a three-dimensional multi-chip array package wherein master semiconductor substrate is formed having a peripheral inner row of contact pads and a peripheral outer row of terminal pads. A plurality of subordinate semiconductor substrates are formed provided with a peripheral row of contact pads that match the contact pads on the master substrate. Openings are formed through centers of the contact pads that extend through the subordinate substrates. The subordinate substrates are stacked on the master substrate with the openings in alignment over the contact pads. The openings are then filled with a conductive material to interconnect the contact pads on all its substrates.