Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure.

Abstract: An SVC compensation strategy optimization method, comprising: calculating a weak voltage node in a fault state based on risk measure; calculating the weak voltage node in a normal state based on a static stability margin; and determining an optimal SVC distribution point and calculating the optimal configuration of SVC capacity. The SVC compensation strategy optimization method overcomes the defects in the prior art, such as low reliability, low optimization precision, poor applicability, etc., and has the advantages of high reliability, high optimization precision, and good applicability.

Abstract: A tumbler with a bi-layer structure has a collision-resistant outer tumbler body, a glass inner container and a lid. The collision-resistant outer tumbler body is made of plastic. The glass inner container is made of glass, is mounted in the collision-resistant outer tumbler body to form a bi-layer structure, and has a container space. The lid is mounted on the collision-resistant outer tumbler body and the glass inner container and has a combining base combined with the collision-resistant outer tumbler body and the glass inner container, an opening unit mounted in the combining base and communicating with the container space, and a closing cap combined with the combining base and selectively closing the opening unit.

Abstract: An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate.

Abstract: Method and system of interferometrically measuring, in reflection, a non-spherical surface with two diffracted beams (of different diffraction orders) formed by a diffractive element positioned transversely to the axis of a common-path interferometer. The first diffracted beam substantially maintains the wavefront of a beam incident onto the diffractive element, while the second diffracted beam has a wavefront profile corresponding to the profile of the measured surface. The first diffracted beam may be reflected by the surface in a cat's eye configuration, while the second diffracted beam is reflected by the surface in a confocal configuration. The surface being measured can be modified to substantially balance radiant powers of the first and second diffracted beams upon reflection off the surface.

Abstract: Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

Abstract: A portable electrical device includes a tablet PC, a bottom plate, a support arm and a pivot portion. The tablet PC includes a breach and a first magnetic inducing member arranged inside the breach. One end of the support arm is pivoted to the bottom plate, and the other end of the support arm is pivoted to the pivot portion, and the other end of the pivot portion is with a second magnetic inducing member. When the second magnetic inducing member is moved into the breach to magnetize the first magnetic inducing member, the tablet PC is securely coupled with the pivot portion so that the tablet PC can be rotated; on the contrary, when the second magnetic inducing member is removed from the breach, the tablet PC can be totally independent to the support arm and the bottom plate.

Abstract: A cross-cut tester includes a handle with a receiving cavity, and a plurality of blades received in the receiving cavity. One end of the handle defines an opening. The cross-cut tester further includes a plurality of gaskets received in the receiving cavity. The gaskets and the blades are positioned one-by-one, and are detachably fixed in the receiving cavity. The cross-cut tester of the present disclosure can effectively improve the efficiency of drawing lines and reduce the cost.

Abstract: The integrated circuit (IC) device includes a substrate, an isolation feature, a first gate structure, a second gate structure, a first contact feature and a first supplementary active region. The isolation feature is disposed in the substrate, and the isolation feature defines a boundary between a first active region and a second active region of the substrate. The first gate structure is disposed over the first active region. The second gate structure is disposed over the second active region. The first contact feature is disposed over the first active region, in which a portion of the first active region is disposed between the first gate structure and the isolation feature. The first supplementary active region is disposed adjacent to the portion of the first active region, in which a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm.

Abstract: Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.

Abstract: Method and system of interferometrically measuring, in reflection, a non-spherical surface with two diffracted beams (of different diffraction orders) formed by a diffractive element positioned transversely to the axis of a common-path interferometer. The first diffracted beam substantially maintains the wavefront of a beam incident onto the diffractive element, while the second diffracted beam has a wavefront profile corresponding to the profile of the measured surface. The first diffracted beam may be reflected by the surface in a cat's eye configuration, while the second diffracted beam is reflected by the surface in a confocal configuration. The surface being measured can be modified to substantially balance radiant powers of the first and second diffracted beams upon reflection off the surface.

Abstract: A method of preparing a porous graphene oxide material. The method includes the steps of: (1) preparing graphene oxide sheets from graphite at 40 to 170° C.; (2) providing a graphene oxide suspension containing the graphene oxide sheets; (3) heating the graphene oxide suspension with a base at 25 to 300° C. for 0.1 to 48 hours to obtain base-treated graphene oxide sheets; and (4) heating a mixture of the base-treated graphene oxide sheets and an acid at 25 to 300° C. for 0.1 to 48 hours to yield the porous graphene oxide material. Also disclosed are novel porous graphene oxide materials and methods of using these materials as catalysts.

Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.

Abstract: The present invention is to provide an LED driver circuit which includes a capacitor and at least one LED respectively connected in parallel to a power source through a switch device, and a controller having an input end connected to a line between the switch device and the power source and being configured for detecting an input voltage applied to the LED. When the controller detected that the input voltage is unable to drive the LED to emit light, the controller activates the switch device to make only the connection between the capacitor and the at least one LED, such that the capacitor discharges a voltage stored therein to the at least one LED to continuously emit light. Since the driver circuit only needs a small-capacity, low-cost capacitor for increasing the light emission time of the at least one LED, the cost of the driver circuit can be lowered effectively.

Abstract: Method and system of interferometrically measuring, in reflection, a non-spherical surface with two diffracted beams (of different diffraction orders) formed by a diffractive element positioned transversely to the axis of a common-path interferometer. The first diffracted beam substantially maintains the wavefront of a beam incident onto the diffractive element, while the second diffracted beam has a wavefront profile corresponding to the profile of the measured surface. The first diffracted beam may be reflected by the surface in a cat's eye configuration, while the second diffracted beam is reflected by the surface in a confocal configuration. The surface being measured can be modified to substantially balance radiant powers of the first and second diffracted beams upon reflection off the surface.

Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.

Abstract: A switch circuit comprises an unidirectional power source module, an unidirectional load module, an inductor and a switch module. By controlling a switching operation of the switch module, the inductor is enabled to store or discharge the electrical energy so as to modulate the operating current. When the inductor supplies the electrical energy to the unidirectional load module, the inductor and the unidirectional load module consist of a loop. When the input voltage is at a higher potential, the switch circuit may control the operating current by the inductor's properties so as to modulate the operating power of the unidirectional load module, and when the input voltage is at a lower potential, the switch circuit still may store or discharge the electrical energy by switching the inductor so as to provide the operating current to the unidirectional load module.

Abstract: An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate.

Abstract: Embodiments of the disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.

Abstract: A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.