Patents by Inventor Chen Wang

Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404875
    Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.
    Type: Application
    Filed: July 12, 2024
    Publication date: December 5, 2024
    Inventors: Sheng-Chen Wang, Kai-Hsuan Lee, Sai-Hooi Yeong, Chia-Ta Yu, Han-Jong Chia
  • Publication number: 20240403118
    Abstract: Computer-implemented methods for deploying workloads in a cloud computing system based on energy efficiency are provided. Aspects include obtaining an energy efficiency metric for a plurality of compute nodes in the cloud computing environment and classifying the plurality of compute nodes into energy efficiency groups based on the energy efficiency metrics. Aspects also include creating a partition of nodes including one compute node selected from each of the energy efficiency groups, deploying a replica of a workload to each compute node in the partition, and monitoring an energy consumption and a computing performance of each of compute node in the partition during a probing period. Aspects further include identifying, based on the energy consumption and performance, a selected energy efficiency group from the plurality of energy efficiency groups and deploying the workload to one or more of the plurality of compute nodes in the selected energy efficiency group.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Inventors: Chen Wang, Huamin Chen
  • Publication number: 20240395607
    Abstract: A semiconductor device includes source/drain contacts, a gate structure, a gate dielectric cap, an etch stop layer, and a gate contact. The source/drain contacts are over a substrate. The gate structure is laterally between the source/drain contacts. The gate dielectric cap is over the gate structure and in contact with the source/drain contacts. The etch stop layer is over the source/drain contacts and the gate dielectric cap. The etch stop layer has an oxidized region directly above the gate dielectric cap. The gate contact extends through the etch stop layer and the gate dielectric cap to the gate structure. The gate contact and the oxidized region of the etch stop layer form an interface perpendicular to the substrate.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih HSIUNG, Yi-Chun CHANG, Jyun-De WU, Yi-Chen WANG, Yuan-Tien TU, Huan-Just LIN
  • Publication number: 20240389336
    Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and memory devices is provided. The semiconductor substrate includes first transistors, and the first transistors are negative capacitance field effect transistors. The interconnect structure is disposed over the semiconductor substrate and electrically connected to the first transistors, and the interconnect structure includes stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers. The memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Chao-I Wu
  • Publication number: 20240386548
    Abstract: The present application related to a method for deleting redundant images of an endoscope. Firstly, a host receives an input image datum from an endoscopy, hereby, capturing a plurality of corresponded input images from the input image data. Next, a plurality of dimension reduction data are obtained to operate with at least one adjacent dimension reduction datum, and then, a plurality of root mean squared error values are obtained to compare with an error threshold value. Hereby, at least one image unarrived the error threshold value are deleted to obtain a plurality of screened images. Thus, redundant images in the input image data of the endoscopy will be deleted to prevent from performing an image analysis of same images or approximated images.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 21, 2024
    Inventors: HSIANG-CHEN WANG, YU-MING TSAO, ARVIND MUKUNDAN
  • Publication number: 20240387266
    Abstract: Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Publication number: 20240389334
    Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240383177
    Abstract: A method of producing a container product comprises providing a mold including a first part and a second part. The mold is closed to define a cavity having a first area and a second area. A molten plastic composition including a polymer and a physical blowing agent is filled into the cavity. Then, the molten plastic composition in the cavity is cooled, such that the molten plastic composition in the first area is completely cooled and solidifies or a central portion of the first area has micro uncooled molten plastic composition. The second area has the plastic composition in the molten state. The first part of the mold is moved in the axial direction. The molten plastic composition in the second area forms a beehive foam after foaming and expansion. Then, the foamed container product in the mold is cooled to take shape and then removed after opening the mold.
    Type: Application
    Filed: May 17, 2023
    Publication date: November 21, 2024
    Inventor: Chih-Chen Wang
  • Publication number: 20240389338
    Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking 10 structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Chun-Fu Cheng, Feng-Cheng Yang, Sheng-Chen Wang, Yu-Chien Chiu, Han-Jong Chia
  • Patent number: 12148505
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12146354
    Abstract: A hinge device includes a pivot seat, a rotating shaft, a first friction block, and a locking assembly. By being structurally provided with a sleeve, a first cam ring, a first elastic ring, a second friction block, a second cam ring, a second elastic ring, an elastic element, a locking portion, and a cover of the locking assembly, the hinge device has a locking function and a long service life.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: November 19, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Chun-Fu Chang, Hui-Chen Wang, Yi-Chun Tang
  • Publication number: 20240381656
    Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Han-Jong Chia, Chung-Te Lin, Feng-Cheng Yang, Meng-Han Lin, Sheng-Chen Wang
  • Publication number: 20240376627
    Abstract: An electroplating device includes a process chamber, a paddle plate and a driving mechanism. The driving mechanism is used for driving the paddle plate to move back and forth to make the paddle plate stir the electroplating solution in the process chamber when a substrate is electroplated. The electroplating device further includes a cleaning assembly and a connecting bracket. The cleaning assembly is used for spraying a cleaning solution onto the electroplated substrate. One end of the connecting bracket is connected to the paddle plate, and the other end of the connecting bracket is connected to the driving mechanism, and the driving mechanism drives the paddle plate to move back and forth via the connecting bracket. The connecting bracket is opened with a hollowed-out area, and the cleaning solution sprayed onto the substrate is collected after passing through the hollowed-out area.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 14, 2024
    Applicant: ACM RESEARCH (SHANGHAI), INC.
    Inventors: Jian Wang, Chen Wang, Hongchao Yang, Chenhua Lu, Jiaqi Li, Zhaowei Jia, Ling Qin, Hui Wang
  • Publication number: 20240381652
    Abstract: In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Sai-Hooi Yeong, Chi On Chui, Sheng-Chen Wang
  • Patent number: 12138751
    Abstract: An impact tool includes an impact assembly and a housing. The impact assembly is used for applying an impact force to an output shaft and includes a main shaft driven by a drive shaft, an impact block connected to the main shaft, and a hammer anvil mating with and struck by the impact block. A motor is at least partially accommodated in the housing. A length L from a rear end of the housing to a front end of the output shaft is greater than or equal to 78 mm and less than or equal to 97 mm and an outer circumferential diameter D of the housing is less than or equal to 60 mm.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: November 12, 2024
    Assignee: Nanjing Chervon Industry Co., Ltd.
    Inventors: Rui Xu, Yuyi Zheng, Chen Wang, Masatoshi Fukinuki, Biao Zhang, Hongtao Ke, Hengyong Hu, Chuan Geng, Xiaoyong Wang, Di Wu
  • Publication number: 20240371956
    Abstract: A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Publication number: 20240366535
    Abstract: A formulation comprising TML-6 or a pharmaceutically acceptable salt, solvate, hydrate, or prodrug thereof in an amorphous form, and one or more excipients,
    Type: Application
    Filed: May 3, 2024
    Publication date: November 7, 2024
    Inventors: Hui-Chen WANG, Chia-Yu HSU, Ling-Ying LIAW
  • Patent number: 12136808
    Abstract: A photovoltaic power generation system includes an inverter, a controller, and at least two direct current branch circuits. The leakage current detection apparatus is configured to: detect a leakage current of the direct current branch circuit on which the leakage current detection apparatus is located and send the leakage current to the controller. The controller is further configured to: when the photovoltaic power generation system runs and a value of a leakage current of the direct current branch circuit exceeds a preset range, determine that an insulation fault occurs on the direct current branch circuit. The system can determine the direct current branch circuit on which the insulation fault occurs in the photovoltaic power generation system, so that measures are taken in time for the direct current branch circuit on which the insulation fault occurs, to eliminate a potential safety hazard.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: November 5, 2024
    Assignee: HUAWEI DIGITAL POWER TECHNOLOGIES CO., LTD.
    Inventors: Yongbing Gao, Chen Wang, Tiansan Lin, Yang Hu
  • Publication number: 20240362785
    Abstract: The present invention provides a method for detecting tissue hemorrhage with image analysis. A host produces a plurality of hyperspectral image information according to a plurality of reference images. An image extraction unit extracts an input image to the host. The host transforms the input image according to the plurality of hyperspectral image information to produce a hyperspectral input image. The host produces an input image spectrum according to the hyperspectral input image. The host performs a feature operation on the input image spectrum according to a preset cell band corresponding to a surface cell of small intestine for generating a plurality of corresponding feature bands. The host performs at least one convolution operation on the plurality of feature bands according to a plurality of kernels for producing a convolution result.
    Type: Application
    Filed: July 20, 2023
    Publication date: October 31, 2024
    Inventors: HSIANG-CHEN WANG, YU-MING TSAO, BING-HSUAN LIANG
  • Publication number: 20240359288
    Abstract: A method of using a polishing pad includes applying a slurry in a first region of the polishing pad. The method further includes spreading the slurry across the first region of the polishing pad at a first rate. The method further includes spreading the slurry across a second region at a second rate different from the first rate, wherein the second region is farther from a center of the polishing pad than the first region. The method further includes spreading the slurry across a third region at a third rate different from the second rate, wherein the second region is between the third region and the first region.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: ChunHung CHEN, Jung-Yu LI, Sheng-Chen WANG, Shih-Sian HUANG