Patents by Inventor Chen Wang

Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12132995
    Abstract: An example apparatus for enhancing video includes a decoder to decode a received 360-degree projection format video bitstream to generate a decoded 360-degree projection format video. The apparatus also includes a viewport generator to generate a viewport from the decoded 360-degree projection format video. The apparatus further includes a convolutional neural network (CNN)-based filter to remove an artifact from the viewport to generate an enhanced image. The apparatus further includes a displayer to send the enhanced image to a display.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Huan Dou, Lidong Xu, Xiaoxia Cai, Chen Wang, Yi-Jen Chiu
  • Patent number: 12133355
    Abstract: A structure for mounting a cooling fan easily and conveniently and in the correct orientation only includes a chassis and at least one fan module. The chassis has a block, a first nut, and a second nut. The fan module has at least one accessory. The block is mounted on the first nut or the second nut. When the block is fixed on the first nut, the fan module can only be placed and installed so as to blow air into the chassis, and when the block is fixed on the second nut, the fan module can only be installed so as to extract air out of the chassis, thereby ensuring the correct mode of operation. An electronic device and a server using the structure is also disclosed.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: October 29, 2024
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Pao-Ching Wang, Wen-Chen Wang
  • Patent number: 12128522
    Abstract: A method includes supplying slurry onto a polishing pad; holding a wafer against the polishing pad with a piezoelectric layer interposed vertically between a pressure unit and the wafer; exerting a force on the piezoelectric layer using the pressure unit to make the piezoelectric layer directly press the wafer; generating, using the piezoelectric layer, a first voltage corresponding to a first portion of the wafer and a second voltage corresponding to a second portion of the wafer; tuning the force exerted on the piezoelectric layer according to the first voltage and the second voltage; and polishing, using the polishing pad, the wafer.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Bin Hsu, Ren-Guei Lin, Feng-Inn Wu, Sheng-Chen Wang, Jung-Yu Li
  • Publication number: 20240357834
    Abstract: A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Bo-Feng Young, Yu-Ming Lin, Han-Jong Chia, Sheng-Chen Wang, Sai-Hooi Yeong
  • Publication number: 20240355063
    Abstract: An input video item that includes a target visual augmentation is accessed. A machine learning model uses the input video item to generate an embedding. The embedding may comprise a vector representation of a visual effect of the target visual augmentation. The machine learning model is trained, in an unsupervised training phase, to minimize loss between training video representations generated within each of a plurality of training sets. Each training set comprises a plurality of different training video items that each include a predefined visual augmentation. Based on the generation of the embedding of the input video item, the target visual augmentation is mapped to an augmentation identifier.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Inventors: Zhenpeng Zhou, Patrick Poirson, Maksim Gusarov, Chen Wang, Oleg Tovstyi
  • Publication number: 20240357828
    Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.
    Type: Application
    Filed: June 30, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chen Wang, Meng-Han Lin, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
  • Patent number: 12119386
    Abstract: A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 12115767
    Abstract: A pad removal method includes affixing a first end of a pad guide to a first location of a pad. The method further includes affixing a second end of the pad guide to a second location of the pad. The method further includes moving the first end from a first position, a first distance from the second location, to a second position, a second distance from the second location, wherein the first distance is greater than a diameter of the pad, and the second distance is less than the width of the pad.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chunhung Chen, Sheng-Chen Wang
  • Publication number: 20240340332
    Abstract: Provided are request processing method, network node, and computer-readable storage medium. The method for I-CSCF includes receiving a first registration refresh request transmitted by P-CSCF, the first registration refresh request is generated by P-CSCF based on a second registration refresh request transmitted by UE, and the first registration refresh request includes historical registration information corresponding to UE. The historical registration information carries address information of a registration server that is cached by P-CSCF in the case that a last registration is successful. Transmitting the first registration refresh request to S-CSCF based on the historical registration information in the first registration refresh request. The influence of situations such as signaling surge, congestion, and service interruption, etc., on request processing can be overcome, network robustness can be improved, and network performance can be optimized, thereby ensuring normal network service.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 10, 2024
    Inventors: Shirong ZHAO, Wenjie LING, Chen WANG
  • Publication number: 20240334638
    Abstract: A functional module securing device and a data processing equipment, including a securing rack including a mounting area, the mounting area places a functional module; a limit piece slidably arranged on an exterior of the securing rack and at least partially located in the mounting area; and a linkage piece arranged on the exterior of the securing rack and connected to the limit piece. The linkage piece configured to drive the limit piece to move along a first direction to at least partially insert the limit piece into a slot of the functional module, or to separate the limit piece from the slot of the functional module. The linkage piece further configured to drive the limit piece to move along a second direction to drive the functional module to at least partially slide out of the mounting area when the limit piece is in the slot of the functional module.
    Type: Application
    Filed: October 9, 2023
    Publication date: October 3, 2024
    Inventors: JIA-FENG LIN, WEN-CHEN WANG
  • Publication number: 20240331754
    Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chao-I Wu, Sheng-Chen Wang, Yu-Ming Lin
  • Patent number: 12107003
    Abstract: A semiconductor device includes a gate structure, source/drain regions, source/drain contacts, a gate dielectric cap, an etch stop layer, and a gate contact. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The source/drain contacts are over the source/drain regions, respectively. The gate dielectric cap is over the gate structure and has opposite sidewalls interfacing the source/drain contacts.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih Hsiung, Yi-Chun Chang, Jyun-De Wu, Yi-Chen Wang, Yuan-Tien Tu, Huan-Just Lin
  • Patent number: 12107007
    Abstract: Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 12106244
    Abstract: A method includes acquiring a to-be-used execution project flow, where the to-be-used execution project flow includes multiple to-be-used flow nodes; in response to detecting that an operation on at least one to-be-used flow node is a preset operation, updating the to-be-used execution project flow; and in response to detecting that a target control is triggered, using the updated to-be-used execution project flow as a target execution project flow.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: October 1, 2024
    Assignee: Beijing Zitiao Network Technology Co., Ltd.
    Inventors: Tao Hong, Dian Xiong, Chen Wang, Linxuan Shi
  • Publication number: 20240309985
    Abstract: The present disclosure relates to a precast base. The precast base comprises a precast concrete body, a plurality of corrugated steel pipes, and a lifting part. The precast concrete body comprises a top surface, a bottom surface opposite to the top surface, and a plurality of mounting holes, each of which penetrates from the top surface to the bottom surface of the precast concrete body. The plurality of corrugated steel pipes are respectively embedded in the plurality of mounting holes. The lifting part is embedded in the top surface of the precast concrete body and is close to the center of the top surface.
    Type: Application
    Filed: October 18, 2023
    Publication date: September 19, 2024
    Inventors: Samuel YIN, Tzu-Liang WU, Jui-Chen WANG, Jhih-Syuan CHEN
  • Publication number: 20240312830
    Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Han-Jong Chia, Meng-Han Lin, Sheng-Chen Wang, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240311264
    Abstract: Computer-implemented methods for estimating the energy consumption of a workload in a Cloud computing system are provided. Aspects include receiving a request for an estimated energy consumption of the workload and obtaining characteristics of the Cloud computing system executing the workload. Aspects also include identifying and employing a unified power consumption model from a power model database based on the characteristics and calculating the estimated energy consumption of the workload based on the unified power consumption model.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Inventors: Eun Kyung Lee, SUNYANAN CHOOCHOTKAEW, Tamar Eilam, MARCELO CARNEIRO DO AMARAL, Huamin Chen, Chen Wang
  • Publication number: 20240312833
    Abstract: A semiconductor structure includes a contact plug on a source/drain region of a transistor, and a via on the contact plug. The via includes a lower portion and an upper portion over the lower portion, the lower portion of the via tapers upward, and the upper portion of the via tapers downward. The semiconductor structure further includes a metal line on the via.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Chih HSIUNG, Jyun-De WU, Yi-Chun CHANG, Yi-Chen WANG, Yuan-Tien TU
  • Publication number: 20240307318
    Abstract: Disclosed herein is a composition comprising a lipid nanoparticle and a double-stranded oligodeoxynucleotide (dsODN) encapsulated in the lipid nanoparticle. According to the embodiments of the present disclosure, the dsODN comprises two strands complementary to each other, in which the first strand comprises the nucleotide sequence of SEQ ID NO: 1. Also disclosed herein are methods of treating cancers by using the present composition.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 19, 2024
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yan-Shen SHAN, Chang-Jung CHEN, Hao-Chen WANG
  • Publication number: 20240314041
    Abstract: Embodiments of the present disclosure provide a node state determination method and apparatus, an electronic device, and a storage medium. The method includes: determining node attribute information of a linkage process node in response to determining a current process node as the linkage process node; determining at least one third-party platform based on the node attribute information, and sending task information corresponding to the linkage process node to the at least one third-party platform, such that the at least one third-party platform processes the task information; and receiving feedback information from the at least one third-party platform, and updating a node state of the current process node to a target state based on the feedback information.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Tao HONG, Dian XIONG, Chen WANG, Linxuan SHI