Abstract: The present disclosure provides a non-contact neck-based respiratory and pulse signal detection method and apparatus, and an imaging device. The method includes: acquiring 3D morphological information of a neck of a human body in real-time; and acquiring a respiratory signal and an electrocardiogram signal of the human body on the basis of the 3D morphological information of the neck.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.

Abstract: A method for fabricating a semiconductor device to account for misalignment includes forming a top via on a first conductive line formed on a substrate, forming liners each using a first dielectric material, including forming first and second liners to a first height along sidewalls of the top via, forming dielectric layers, including forming first and second dielectric layers on the first conductive line to the first height and adjacent to the first and second liners, respectively, recessing the top via to a second height, and forming an additional dielectric layer on the recessed top via to the first height using a second dielectric material. The first and second dielectric materials are selected to compensate for potential misalignment between the first conductive line and the top via.

Abstract: A method of forming a semiconductor structure includes forming vertical fins comprising a first semiconductor layer, an isolation layer and a second semiconductor layer, the first and second semiconductor layers providing vertical transport channels for lower and upper vertical transport field-effect transistors (VTFETs) of a stacked VTFET structure. The method also includes forming a first gate stack for the lower VTFET surrounding a first portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack for the upper VTFET surrounding a second portion of the second semiconductor layer of the vertical fins. The first and second portions have different sizes such that the upper and lower VTFETs of the stacked VTFET structure have different effective gate widths.

Abstract: Provided is a process executed by a robot, including: traversing, to a first position, a first distance in a backward direction; after traversing the first distance, rotating 180 degrees in a first rotation; after the first rotation, traversing, to a second position, a second distance in the second direction; and after traversing the second distance, rotating 180 degrees in a second rotation such that the field of view of the sensor points in the first direction.

Abstract: Provided are operations including: receiving, with one or more processors of a robot, an image of an environment from an imaging device separate from the robot; obtaining, with the one or more processors, raw pixel intensity values of the image; extracting, with the one or more processors, objects and features in the image by grouping pixels with similar raw pixel intensity values, and by identifying areas in the image with greatest change in raw pixel intensity values; determining, with the one or more processors, an area within a map of the environment corresponding with the image by comparing the objects and features of the image with objects and features of the map; and, inferring, with the one or more processors, one or more locations captured in the image based on the location of the area of the map corresponding with the image.

Abstract: Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a second mask layer are formed on each fin. A spacer layer is formed on the source/drain region and between each fin, and a dielectric layer is formed on the spacer layer and along an exterior of each fin. A plurality of gate metal portions is created each having a thickness about equal to a target thickness. The first mask layer and an exposed portion of the dielectric layer are removed from each fin. An interlayer dielectric is deposited on the semiconductor structure. Portions of the interlayer dielectric and the gate metal are removed to a top of the second mask layer. The gate metal portions are each recessed to substantially the same depth.

Abstract: Techniques regarding anchors for fins comprised within stacked VTFET devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can further comprise a fin extending from a semiconductor body. The fin can be comprised within a stacked vertical transport field effect transistor device. The apparatus can also comprise a dielectric anchor extending from the semiconductor body and adjacent to the fin. Further, the dielectric anchor can be coupled to the fin.

Abstract: Structures and methods that facilitate forming isolated contacts in stacked vertical transport field effect transistors (VTFETs). A pair of stacked VTFETs are formed on a substrate and isolated from each other. A via or hole is formed to extend to a drain of the second VTFET and a source of the first VTFET. The via is filled with a metal below the first VTFET to form the second contact. The second contact is capped with a non-conductive material and the remaining portion of the via is filled with metal to form the first contact. Alternatively, a via or hole is formed to extend to a source of the second VTFET and a source of the first VTFET. The second contact may serve as a local interconnect, a ground, or a voltage source connection.

Abstract: A method of forming a semiconductor structure includes forming vertical fins comprising a first semiconductor layer, an isolation layer and a second semiconductor layer, the first and second semiconductor layers providing vertical transport channels for lower and upper vertical transport field-effect transistors (VTFETs) of a stacked VTFET structure. The method also includes forming a first gate stack for the lower VTFET surrounding a first portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack for the upper VTFET surrounding a second portion of the second semiconductor layer of the vertical fins. The first and second portions have different sizes such that the upper and lower VTFETs of the stacked VTFET structure have different effective gate widths.

Abstract: A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.

Abstract: A hitch assist system and method are provided herein. A human machine interface is configured to receive user-input specifying a target travel direction of a vehicle. A controller is configured to generate commands for autonomously maneuvering the vehicle in the target travel direction, identify a hitch coupler of a trailer based on input received from an object detection system, and request additional user-input updating the target travel direction if the hitch coupler is unable to be identified.

Abstract: A method and device for controlling a vehicle, and an autonomous driving vehicle are provided. The method includes that: historical weather information of a present driving road planned for a vehicle is acquired; a slippery parameter of the present driving road is determined according to the historical weather information; and an autonomous driving mode of the vehicle is controlled according to the slippery parameter.

Abstract: Techniques for forming VFETs with differing gate lengths Lg on the same wafer using a gas cluster ion beam (GCIB) process to produce fins of differing heights are provided. In one aspect, a method of forming fins having different heights includes: patterning the fins having a uniform height in a substrate, the fins including at least one first fin and at least one second fin; forming an oxide at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation); and removing the oxide from the base of the at least one second fin to reveal the at least one first fin having a height H1 and the at least one second fin having a height H2, wherein H2>H1. VFETs and methods for forming VFETs having different fin heights using this process are also provided.

Abstract: A semiconductor device includes a vertical transistor on a substrate. The vertical transistor includes at least one fin. A bottom source/drain is disposed on the substrate and around the at least one fin. A spacer layer is disposed on the bottom source/drain and around the at least one fin. A gate structure is disposed on the spacer layer and around the at least one fin. The gate length is the same or substantially the same on each side of the at least one fin.

Abstract: A method for manufacturing a semiconductor device includes forming a first field-effect transistor (FET) on a substrate, the first FET comprising a first plurality of channel regions extending in a first direction, and stacking a second FET on the first FET, the second FET comprising a second plurality of channel regions extending in a second direction perpendicular to the first direction, wherein the first FET comprises a first gate region extending in the second direction across the first plurality of channel regions, and the second FET comprises a second gate region extending in the first direction across the second plurality of channel regions.

Abstract: Provided are a control method and system for enhancing an endurance capability to an abnormal voltage of a wind turbine generator system. The control method, includes; providing a doubly-fed wind turbine generator system connected to a power grid; detecting a voltage of the power grid, and determining whether the voltage of the power grid has a fault; when the voltage of the power grid has a fault, detecting a voltage of the DC buses, and determining whether the voltage of the DC buses exceeds a limit value; when the voltage of the DC buses exceeds the limit value, performing integrated system coordination control according to an abnormal operating condition mode; and when the voltage of the power grid returns to a normal range, performing integrated system coordination control according to a normal operating condition mode.

Abstract: A semiconductor wafer includes a substrate. The substrate includes a first substrate region doped with a first dopant and a second substrate region doped with a second dopant. The semiconductor wafer further includes a buried oxide (BOX) layer formed on the substrate and a channel layer formed above the BOX layer. A first transistor is operably disposed on the substrate in the first substrate region and a second transistor is operably disposed on the substrate in the second substrate region. First doped source and drain structures electrically connected to the substrate in the first substrate region and separated by portions of the channel layer and the BOX layer. Second doped source and drain structures electrically connected to the substrate in the second substrate region and separated by portions of the channel layer and the BOX layer.

Abstract: A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure and a sacrificial layer in contact with a source/drain region of the stacked vertical transport field-effect transistor structure. A masking layer is formed over the sacrificial layer. The masking layer defines a pattern to be patterned into the sacrificial layer. The sacrificial layer is patterned based on the masking layer to form a patterned sacrificial layer and the masking layer is removed. A portion of the stacked VTFET structure is etched down to a surface of the patterned sacrificial layer and the patterned sacrificial layer is removed to form a channel exposing the source/drain region. A contact material is formed in the etched portion of the stacked vertical transport field-effect transistor structure and in the channel. The contact material is formed in contact with the exposed source/drain region.

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other.