Patents by Inventor Chen Zhang

Chen Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200295132
    Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Chen ZHANG, Peng XU, Chun Wing YEUNG
  • Patent number: 10777468
    Abstract: A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure and a sacrificial layer in contact with a source/drain region of the stacked vertical transport field-effect transistor structure. A masking layer is formed over the sacrificial layer. The masking layer defines a pattern to be patterned into the sacrificial layer. The sacrificial layer is patterned based on the masking layer to form a patterned sacrificial layer and the masking layer is removed. A portion of the stacked VTFET structure is etched down to a surface of the patterned sacrificial layer and the patterned sacrificial layer is removed to form a channel exposing the source/drain region. A contact material is formed in the etched portion of the stacked vertical transport field-effect transistor structure and in the channel. The contact material is formed in contact with the exposed source/drain region.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Tenko Yamashita, Kangguo Cheng, Oleg Gluschenkov
  • Patent number: 10773597
    Abstract: An autonomous vehicle controller includes a memory and a processor programmed to execute instructions stored in the memory. The instructions include determining a plurality of energy cost functions. Each energy cost function is associated with a combination of candidate variables. The instructions further include selecting one of the plurality of energy cost functions as a minimum energy cost function, determining a combination of candidate variables associated with the minimum energy cost function, and controlling acceleration of a host vehicle according to the combination of candidate variables associated with the minimum energy cost function.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: September 15, 2020
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Yanan Zhao, Chen Zhang, Ming Lang Kuang
  • Publication number: 20200286793
    Abstract: Techniques facilitating forming a backside ground or power plane in stacked vertical transport field effect transistor are provided. A semiconductor structure can comprise a first field effect transistor (FET). The semiconductor structure can also comprise a second FET. The first FET can be vertically stacked on a first surface of the second FET. The second FET can be electrically coupled to a conductive plane on a second surface of the second FET, the second surface being opposite to the first surface.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 10, 2020
    Inventors: Chen Zhang, Tenko Yamashita, Kangguo Cheng, Lawrence A. Clevenger
  • Publication number: 20200286788
    Abstract: A method is presented for constructing mechanically stable fins. The method includes forming a fin stack including a plurality of sacrificial layers, recessing the fin stack to form channel fins, depositing a first type epitaxy between the channel fins, depositing a dielectric region over the first type epitaxy, depositing a second type epitaxy over the dielectric region, and removing the plurality of sacrificial layers resulting in formation of a plurality of gaps. The method further includes filling a first set of the plurality of gaps with a p-type work function metal (WFM) to form a p-type field effect transistor (pFET) structure and filling a second set of the plurality of gaps with an n-type WFM to form an n-type field effect transistor (nFET) structure, where the nFET structure is stacked over the pFET structure.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 10, 2020
    Inventors: Ruilong Xie, Alexander Reznicek, Chun-Chen Yeh, Chen Zhang
  • Publication number: 20200288260
    Abstract: An audio processing system and method which calculates, based on spatial metadata of the audio object, a panning coefficient for each of the audio objects in relation to each of a plurality of predefined channel coverage zones. Converts the audio signal into submixes in relation to the predefined channel coverage zones based on the calculated panning coefficients and the audio objects. Each of the submixes indicating a sum of components of the plurality of the audio objects in relation to one of the predefined channel coverage zones. Generating a submix gain by applying an audio processing to each of the submix and controls an object gain applied to each of the audio objects. The object gain being as a function of the panning coefficients for each of the audio objects and the submix gains in relation to each of the predefined channel coverage zones.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 10, 2020
    Applicant: Dolby Laboratories Licensing Corporation
    Inventors: Alan J. SEEFELDT, Lie LU, Chen ZHANG
  • Publication number: 20200286831
    Abstract: A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 10, 2020
    Inventors: Dongbing Shao, Chen Zhang, Zheng Xu, Tenko Yamashita
  • Patent number: 10766468
    Abstract: A method of providing an additive offset of a longitudinal acceleration signal of a traveling motor vehicle. The signal being measured by an inertial sensor is ascertained. At least the longitudinal acceleration signal, a braking signal, and a drive signal are detected. A force balance of the longitudinal dynamic of the motor vehicle is analyzed. The signals are detected both during at least one acceleration process as well as during at least one braking process. The signals during the acceleration processes are detected and/or analyzed separately from the signals during the braking processes, and the additive offset is ascertained by comparing the signals detected during the acceleration processes or the values calculated therefrom with the signals detected during the braking processes or the values calculated therefrom. The invention further relates to an electronic controller.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 8, 2020
    Assignee: Continental Teves AG & Co. OHG
    Inventors: Chen Zhang, Julien Levrier
  • Patent number: 10768633
    Abstract: A hitch assist system is provided herein. The hitch assist system includes a sensing system configured to detect a hitch assembly and a coupler. A controller is configured to generate commands for maneuvering a vehicle along a first path or a second path. A user input device includes a display, the display configured to illustrate the first and second paths.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: September 8, 2020
    Assignee: Ford Global Technologies, LLC
    Inventors: Yu Ling, Chen Zhang, Luke Niewiadomski, Theresa Lin, Erick Michael Lavoie
  • Patent number: 10763327
    Abstract: A method of forming a semiconductor structure includes forming outer spacers surrounding a dummy gate, the dummy gate being disposed over a channel stack comprising two or more nanosheet channels and sacrificial layers formed above and below each of the two or more nanosheet channels. The method also includes forming an oxide surrounding the outer spacers, the oxide being disposed over source/drain regions surrounding the channel stack. The method further includes removing the dummy gate, removing the outer spacers, and performing a channel release to remove the sacrificial layers in the channel stack following removal of the outer spacers. The method further includes performing conformal deposition of a dielectric layer and a work function metal on exposed portions of the oxide, and filling a gate metal over the channel stack, the gate metal being surrounded by the work function metal.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chun W. Yeung, Chen Zhang
  • Publication number: 20200273755
    Abstract: A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure including one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower VTFET, an isolation layer, and a second semiconductor layer providing a vertical transport channel for an upper VTFET. The method also includes forming at least one vertical via in the stacked VTFET structure spaced apart from the one or more vertical fins. The method further includes forming at least one horizontal via extending from the vertical via to at least one source/drain region of at least one of the upper and lower VTFETs. The method further includes forming a contact liner in the horizontal via, forming a barrier layer on sidewalls of the vertical via and the contact liner, and forming a contact material over the barrier layer in the vertical via.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 27, 2020
    Inventors: Heng Wu, Tenko Yamashita, Chen Zhang, Joshua M. Rubin
  • Patent number: 10756205
    Abstract: A method of fabricating a semiconductor device includes forming a back gate dielectric. A layer of two-dimensional material is transferred onto a surface of the back gate dielectric. A top gate dielectric is deposited and a top gate formed thereon. A first set of spacers is formed around the top gate and exposed portions of the top gate dielectric removed and a second set of spacers formed around the top gate. Exposed portions of the two-dimensional material are removed. A directional etch down of the substrate and a lateral isotropic etch of the substrate are performed and open spaces filled with a dielectric material surrounding the top gate, the back gate dielectric, and the substrate. The dielectric material is etched from the top gate and the back gate dielectric, the second set of spacers removed, and source and drain contact metal deposited. The source and drain contacts the layer.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Chun Wing Yeung, Chen Zhang
  • Patent number: 10755706
    Abstract: A method and system of controlling a digital assistant with dynamically switchable endpoint devices, comprising: dynamically selecting a respective input endpoint device and a respective controlled device for each of a plurality of voice-based requests from a user to the computing system, including: at a first point in time, acquiring respective instances of a first voice input from a first set of two or more input endpoint devices; obtaining a representative copy of the first voice input based on the respective instances of the first voice input that have been acquired from the first set of two or more input endpoint devices; determining a first actionable intent based on the representative copy of the first voice input; and dispatching a first encoded instruction to a first controlled endpoint device selected from the plurality of controlled endpoint devices in accordance with the first actionable intent.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: August 25, 2020
    Assignee: MIDEA GROUP CO., LTD.
    Inventors: Haibin Huang, Chi Zhang, Xiaofeng Xu, Chen Zhang, Dongyan Wang
  • Publication number: 20200259009
    Abstract: A method of fabricating a semiconductor device includes forming a back gate dielectric. A layer of two-dimensional material is transferred onto a surface of the back gate dielectric. A top gate dielectric is deposited and a top gate formed thereon. A first set of spacers is formed around the top gate and exposed portions of the top gate dielectric removed and a second set of spacers formed around the top gate. Exposed portions of the two-dimensional material are removed. A directional etch down of the substrate and a lateral isotropic etch of the substrate are performed and open spaces filled with a dielectric material surrounding the top gate, the back gate dielectric, and the substrate. The dielectric material is etched from the top gate and the back gate dielectric, the second set of spacers removed, and source and drain contact metal deposited. The source and drain contacts the layer.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 13, 2020
    Inventors: Peng Xu, Chun Wing Yeung, Chen Zhang
  • Patent number: 10741557
    Abstract: A method and structure for forming hybrid high mobility channel transistors. The method includes: providing a substrate, epitaxially growing a buffer layer over the substrate and a semiconductor layer over the buffer layer, forming a partial opening over the semiconductor layer, epitaxially growing a second semiconductor layer in the opening, forming a first plurality of fins from the first semiconductor layer and a second plurality of fins from the second semiconductor layer, where the first semiconductor layer and the second semiconductor material comprise different materials, oxidizing a portion of the second plurality of fins, and stripping the oxidized portion of the second plurality of fins, where after striping the oxidized portion of the second plurality of fins, the second plurality of fins have the same width as the first plurality of fins.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 10740920
    Abstract: Provided is a method including capturing a plurality of images by at least one sensor of a robot; aligning, with a processor of the robot, data of respective images based on an area of overlap between the fields of view of the plurality of images; and determining, with the processor of the robot, based on alignment of the data, a spatial model of the environment.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: August 11, 2020
    Assignee: AI Incorporated
    Inventors: Ali Ebrahimi Afrouzi, Chen Zhang, Sebastian Schweigert
  • Patent number: 10741681
    Abstract: The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chi-Chun Liu, Chun Wing Yeung, Chen Zhang
  • Publication number: 20200251593
    Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: Xin Miao, Kangguo Cheng, Wenyu XU, Chen Zhang
  • Publication number: 20200247819
    Abstract: Disclosed in the present invention are a compound represented by formula (I), a tautomer thereof or a pharmaceutically acceptable salt, and applications thereof in the preparation of drugs for treating HBV-related diseases.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 6, 2020
    Inventors: Haiying He, Jing Wang, Zhigan Jiang, Yaxun Yang, Peng Shao, Chen Zhang, Jian Li, Shuhui Chen
  • Patent number: 10734501
    Abstract: A method for manufacturing a semiconductor device includes forming a channel layer on a semiconductor substrate and forming at least two spacers on the channel layer. A first portion of a gate metal layer is formed between the spacers, and a dielectric layer is conformally deposited on the spacers and the first portion of the gate metal layer. In the method, part of the dielectric layer is directionally removed from surfaces which are parallel to an upper surface of the substrate. A second portion of the gate metal layer is formed between remaining portions of the dielectric layer and on the first portion of the gate metal layer, and a cap layer is deposited on the second portion of the gate metal layer. A lateral width the second portion of the gate metal layer is less than a lateral width of the first portion of the gate metal layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Kangguo Cheng, Chen Zhang, Wenyu Xu