Patents by Inventor Cheng Chen

Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240102959
    Abstract: An IC structure includes a biologically sensitive field-effect transistor (BioBET) in a semiconductor substrate, and a dielectric layer over a backside surface of the semiconductor substrate. The dielectric layer has a sensing well extending through the dielectric layer to a channel region of the BioFET. The IC structure further includes a biosensing film, a plurality of fluid channel walls, and a first heater. The biosensing film lines the sensing well in the dielectric layer. The fluid channel walls are over the biosensing film and define a fluid containment region over the sensing well of the dielectric layer. The first heater is in the semiconductor substrate. The first heater has at least a portion overlapping with the fluid containment region.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Tsun CHEN, Yi-Hsing HSIAO, Jui-Cheng HUANG, Yu-Jie HUANG
  • Publication number: 20240103520
    Abstract: A method of controlling movement of an autonomous mobile apparatus including a driving module, a processor, and a positioning module includes steps of: the processor moving the autonomous mobile apparatus at a default speed from a first location toward a second location along a straight path; the positioning module obtaining data related to a current location; when the processor determines that a distance between the current location and the second location is greater than a predetermined distance, the processor obtaining a deviating direction and a minimum distance of the current location relative to the straight path; the processor setting a movement speed and an angular velocity based on the deviating direction, a tolerant distance, the minimum distance, and the default speed; and the processor controlling the driving apparatus to move the autonomous mobile apparatus at the movement speed and turning the autonomous mobile apparatus at the angular velocity.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Tung CHEN, Chung-Hou WU, Chao-Cheng CHEN, Wen-Wei CHIANG
  • Publication number: 20240104032
    Abstract: The address conversion system includes a storage device, a memory bus, and a processor. The processor is configured to execute the following steps: generating a real buffer on the storage device; generating a fake buffer in a fake capacity of the storage device by a fake buffer algorithm; establishing a coupling relationship between the real buffer and the fake buffer through a coupling algorithm by the coupler of the memory bus; receiving a compressed data from a first device by the real buffer; when a second device wants to read the fake buffer, the coupler guides the second device to the real buffer through the coupling relationship for reading; transmitting the compressed data of the real buffer to the coupler by the memory bus; decompressing the compressed data into a decompressed data by the coupler; and transmitting the decompressed data to the second device by the memory bus.
    Type: Application
    Filed: May 18, 2023
    Publication date: March 28, 2024
    Inventors: Kuo-Jung WU, Yi-Cheng CHEN
  • Patent number: 11938405
    Abstract: An electronic device and a method for detecting abnormal device operation are provided. The method includes: obtaining multiple action events of a movable input device, and each action event including a relative coordinate and a time stamp of the movable input device; generating multiple absolute coordinates based on the relative coordinate of each action event; estimating multiple speed vectors based on the absolute coordinates and the time stamp of each action event; estimating multiple acceleration vectors based on the speed vectors and the time stamp of each action event; and estimating a probability of abnormal operation based on the speed vectors and the acceleration vectors.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: March 26, 2024
    Assignee: Acer Incorporated
    Inventors: Tien-Yi Chi, Wei-Chieh Chen, Shih-Cheng Huang, Tzu-Lung Chuang
  • Patent number: 11939486
    Abstract: An aqueous dispersion of polymeric particles comprising an emulsion polymer and a polyalkylene oxide with a weight average molecular weight in the range of 450 to 1,500 g/mole, and an aqueous coating composition with low VOCs comprising the aqueous dispersion and providing coatings made therefrom with improved water whitening resistance and hardness.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: March 26, 2024
    Assignees: Dow Global Technologies LLC, Rohm and Haas Company
    Inventors: Yan Li, Junyu Chen, Cheng Shen, James C. Bohling, Zhi Juan Gong, Tao Wang
  • Patent number: 11942750
    Abstract: A laser inspection system is provided. A laser source emits a laser with a first spectrum and the laser is transmitted by a first optical fiber. A gain optical fiber doped with special ions is connected to the first optical fiber, and a light detector is provided around the gain optical fiber. When the laser with the first spectrum passes through the gain optical fiber, the gain optical fiber absorbs part of the energy level of the laser with the first spectrum, so that the laser with the first spectrum is converted to generate light with a second spectrum based on the frequency conversion phenomenon. The light detector detects the intensity of the light with the second spectrum, so that the power of the laser source can be obtained.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: March 26, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chi Lee, Hsin-Chia Su, Shih-Ting Lin, Yu-Cheng Song, Fu-Shun Ho, Chih-Chun Chen
  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Patent number: 11942478
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
  • Patent number: 11942543
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Patent number: 11943373
    Abstract: An identity certificate may be issued to a blockchain node. The issuance may include issuing a first identity certificate to a first terminal and receiving a second identity certificate issuance request that is from the first terminal. A second identity certificate may be issued to the first terminal, and a third identity certificate issuance request is received from the second terminal. A third identity certificate is issued to the second terminal, so that the second terminal forwards the third identity certificate to the third terminal.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: March 26, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Mao Cai Li, Zong You Wang, Kai Ban Zhou, Chang Qing Yang, Hu Lan, Li Kong, Jin Song Zhang, Yi Fang Shi, Geng Liang Zhu, Qu Cheng Liu, Qiu Ping Chen
  • Patent number: 11942408
    Abstract: A method includes: bonding a plurality of interposer dies to a first redistribution layer (RDL), each of the interposer dies comprising a substrate and a second RDL below the substrate; encapsulating the first RDL and the interposer dies; reducing a thickness of the substrate of each of the interposer dies; and electrically coupling the interposer dies to a first semiconductor die.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
  • Patent number: 11942513
    Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang
  • Patent number: 11940388
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 26, 2024
    Assignee: IXENSOR CO., LTD.
    Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
  • Patent number: 11939666
    Abstract: Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 26, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xiangjin Xie, Carmen Leal Cervantes, Feng Chen, Lu Chen, Wenjing Xu, Aravind Kamath, Cheng-Hsiung Matthew Tsai, Tae Hong Ha, Alexander Jansen, Xianmin Tang
  • Publication number: 20240094625
    Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Chih-Cheng LIN, Chia-Jen CHEN
  • Publication number: 20240093373
    Abstract: A method for preparing antibacterial stainless steel by surface alloying includes the steps of coating an infiltration promoter layer on a stainless steel surface, coating an antibacterial metal layer on a surface of the infiltration promoter layer, and performing heat treatment of the stainless steel to diffuse an antibacterial metal into the stainless steel. This method can be applied to various types of stainless steel, and the antibacterial metal can be diffused and quenched into the stainless steel, such that the finally formed surface of the stainless steel has an antibacterial alloy layer with a specific thickness to provide better corrosion resistance and antibacterial ability without changing the advantages and properties of the antibacterial metal or stainless steel substrate, and the thickness and concentration of the antibacterial metal layer, and the parameters for heat treatment can be adjusted to control the chemical composition and thickness of the antibacterial alloy layer.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 21, 2024
    Inventors: WEN-TA TSAI, BERNARD HAOCHIH LIU, ZHI-YAN CHEN, CHONG-CHENG HUANG
  • Publication number: 20240096677
    Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20240096864
    Abstract: An optical device includes an optical component and an electrical component. The optical component has a sensing surface and a backside surface opposite to the sensing surface. The electrical component is disposed adjacent to the backside surface of the optical component and configured to support the optical component. A portion of the backside surface of the optical component is exposed from the electrical component.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiang-Cheng TSAI, Ying-Chung CHEN
  • Publication number: 20240098959
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen