Patents by Inventor Cheng Chen

Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250127592
    Abstract: A magnetic traction device for impacted tooth, comprising a first magnetic component fixed to a normal tooth and a second magnetic component fixed to an impacted tooth. There is an attractive magnetic force between the first and second magnetic components, thereby pulling the impacted tooth toward the direction of the normal tooth where the first magnetic component is located.
    Type: Application
    Filed: September 27, 2024
    Publication date: April 24, 2025
    Inventor: LIANG-CHENG CHEN
  • Publication number: 20250129329
    Abstract: A culture medium for hepatoma organoid culture, comprising an MST1/2 kinase inhibitor, at least one cell culture additive selected from N2 and B27, a hepatocyte growth factor, an ITS cell culture additive, Y27632, dexamethasone, Neuregulin-1, insulin, an epidermal cell growth factor, GlutaMAX, and non-essential amino acids. The application further relates to a hepatoma organoid culture method and an application thereof. By using the culture medium for hepatoma organoid, effective and rapid expansion of the hepatoma organoid can be achieved, and the organoid obtained by such expansion maintains the pathological characteristics of a patient, improves the culture success rate and the expansion rate of the hepatoma organoid, and provides a research basis for individualized treatment of the patient.
    Type: Application
    Filed: September 16, 2021
    Publication date: April 24, 2025
    Applicant: PRECEDO PHARMACEUTICALS CO., LTD
    Inventors: Qing Song LIU, Wen Liang Wang, Tao HUANG, Cheng CHEN
  • Publication number: 20250130966
    Abstract: A method of synchronization in a training state of Universal Serial Bus (USB) includes sending SLOS1 ordered sets by a transmitter in a LOCK1 state, receiving the SLOS1 ordered sets by a receiver in the LOCK1 state, stopping the transmitter from sending training ordered sets according to a lane adapter state machine (LASM) if the transmitter sends the training ordered sets in the LOCK1 state continuously in an infinite loop. The training ordered sets include the SLOS1 ordered sets. The method further includes sending new SLOS1 ordered sets by the transmitter, receiving the new SLOS1 ordered sets by a receiver, and the transmitter and the receiver entering a LOCK2 state. The length of the new SLOS1 ordered sets is different from the length of the SLOS1 ordered sets.
    Type: Application
    Filed: October 18, 2023
    Publication date: April 24, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chih-Chieh Wang, Tse-Wei Wang, Yu-Cheng Chen
  • Publication number: 20250133213
    Abstract: The embodiment of the disclosure provides a video encoding method and apparatus, an electronic device and a storage medium. The method includes the steps of determining a video segment included in a target video according to a duration corresponding to a first picture group parameter; determining a target feature corresponding to video encoding data of a previous video segment for a current video segment; inputting the target feature into a target decision model, and determining a picture group parameter corresponding to the current video segment by using the target decision model; and encoding the current video segment based on the picture group parameter corresponding to the current video segment.
    Type: Application
    Filed: October 11, 2024
    Publication date: April 24, 2025
    Inventors: Cheng CHEN, Shu Shi
  • Publication number: 20250132221
    Abstract: An electronic package is provided and includes: a carrier structure, an electronic component disposed on the carrier structure, a heat dissipation structure disposed on the electronic component, a heat conductor sandwiched between the electronic component and the heat dissipation structure, a first intermetallic compound layer formed between the heat dissipation structure and the heat conductor, and a second intermetallic compound layer formed between the heat conductor and the electronic component. Therefore, stable connections can be formed between the heat dissipation structure, the heat conductor and the electronic component via the first intermetallic compound layer and the second intermetallic compound layer to improve heat dissipation effect.
    Type: Application
    Filed: June 26, 2024
    Publication date: April 24, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Dai-Fei LI, Liang-Yi HUNG, Chia-Cheng CHEN, Yu-Po WANG
  • Patent number: 12283609
    Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.
    Type: Grant
    Filed: January 29, 2024
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Chi On Chui
  • Patent number: 12282314
    Abstract: Task assignment for multi-robot systems (MRSs) in a smart factory (Industry 4.0) is described. Aspects are directed to a hypergraph based MRS and production model facilitating the cooperation among robots and serving frequent reconfiguration desired in Industry 4.0. Aspects are directed to a time complexity friendly search algorithm for real-time application using a hypergraph model to get task assignment(s). Parameters are provided for a tradeoff between solution optimality and time complexity. In an implementation, an example system can include a MRS including robots, wherein the MRS is configured to perform a manufacturing task, and a computing device configure to perform a multi-robot task allocation (MRTA) for the MRS. In an implementation, an example method can include generating task assignments, using MRTA, for robots of a MRS including the robots, wherein the MRS is configured to perform a manufacturing task, and providing the task assignments to the MRS.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 22, 2025
    Assignee: University of South Florida
    Inventors: Zixiang Nie, Kwang-Cheng Chen
  • Patent number: 12280889
    Abstract: An aerial vehicle is configured to operate within indoor spaces. The aerial vehicle is programmed with positions of waypoints within three-dimensional space, and to calculate a trajectory for traveling through such waypoints in a manner that minimizes snap of the aerial vehicle. Where a distance between a pair of the waypoints is sufficiently long, the aerial vehicle inserts intervening waypoints for planning purposes, and programs the aerial vehicle to travel at a maximum speed between the intervening waypoints. Upon detecting an obstacle with a first range using one or more sensors, the aerial vehicle reduces its speed and monitors a second, shorter range using the sensors, and compensates for motion between such readings.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 22, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Chong Huang, Yibo Cao, Cheng Chen, Yang Liu, Kah Kuen Fu, Tianyang Ma
  • Patent number: 12283596
    Abstract: A device includes a substrate, a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a bottom dielectric structure. The channel layer is over the substrate. The gate structure is across the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer and are connected to the channel layer. The bottom dielectric structure is between the first source/drain epitaxial structure and the substrate. A maximum width of the first source/drain epitaxial structure is greater than or equal to a maximum width of the bottom dielectric structure in a cross-sectional view.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Pi Tseng, De-Fang Chen, Chao-Cheng Chen
  • Publication number: 20250126837
    Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250124583
    Abstract: An image processing device includes a memory, an image generator and a motion detection circuit. The image generator generates first data based on input image data and stores the first data to the memory. The motion detection circuit detects whether there is a presence of a motion detection event in the input image data.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 17, 2025
    Inventor: Fu-Cheng CHEN
  • Publication number: 20250124602
    Abstract: An image processing device includes a memory, a frame compression circuit, an image processing circuit, an image encoding circuit and a controller. The memory includes a first storage space and a second storage space. The frame compression circuit generates first data based on input image data and stores the first data to the first storage space. The image processing circuit generates second data based on the input image data and stores the second data to the second storage space. The image encoding circuit reads the second data from the second storage space, encodes the second data to generate third data, and stores the third data to the first storage space. The controller outputs the first data and the third data from the first storage space.
    Type: Application
    Filed: September 25, 2024
    Publication date: April 17, 2025
    Inventors: Fu-Cheng CHEN, Jia-Lin DING, Jiang-Nan XIA
  • Publication number: 20250126809
    Abstract: A semiconductor structure including device structures arranged in a stack is provided. The device structures include substrates and through-substrate vias (TSVs). The TSVs are located in the substrates. The TSVs includes first TSVs. Each of the device structures includes the corresponding substrate and the corresponding first TSV. Each of the first TSVs passes through the corresponding substrate. The number of the TSVs in the endmost device structure is less than the number of the TSVs in another of the device structures. The first TSV in the endmost device structure and the first TSV in another of the device structures are aligned with each other and electrically connected to each other.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 17, 2025
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Lin Lu, Chun-Cheng Chen, Ka Man So, Wei-Heng Chen, Shou-Zen Chang
  • Publication number: 20250122917
    Abstract: A flange integrated tuned mass damper, including a main shaft structure, a plurality of wire rope isolators, and a mass ring. Flange plates are installed on the main shaft structure, and the mass ring is located below and connected to the flange plates through the plurality of wire rope isolators uniformly distributed in a circumferential direction. The plurality of wire rope isolators are uniformly distributed outside the main shaft structure in the circumferential direction, and the wire rope isolators directly carries the mass ring and are in a tensile deformation state, with both spring and damper functions. The wire rope isolators can bear tensile, compressive, rolling, and shearing loads, thus ensuring the degree of freedom of the mass ring in any horizontal direction.
    Type: Application
    Filed: October 10, 2024
    Publication date: April 17, 2025
    Inventors: Zhenyu DING, Cheng CHEN, Shijing CAO, Zhiqiang LI
  • Publication number: 20250126758
    Abstract: The present invention provides a rear-door heat dissipation system with a horizontally arranged and series-connected design comprising a heat dissipation cabinet, at least one condenser unit, and a heat dissipation device. The heat dissipation cabinet is provided therein with an active heat source device and a cabinet back door on one side of the heat dissipation cabinet, wherein the cabinet back door is provided with an air circulation unit. The condenser unit is provided on the cabinet back door, comprising a plurality of condensers. Wherein the circulation tube system of each of the condensers comprises a first and second main-channel aluminum tube, and aluminum flat tubes. Each aluminum flat tube has two ends respectively connecting to the first and second main-channel aluminum tube. An airflow channel is formed between each two adjacent aluminum flat tubes to enable air circulation, and each airflow channel is provided with an aluminum fin.
    Type: Application
    Filed: September 3, 2024
    Publication date: April 17, 2025
    Inventors: Cheng-Chien WAN, Cheng-Jui WAN, Chun-Hsien SU, Hui-Fen HUANG, Fong Jou TU, Chi Cheng CHEN, Chuan Meng WANG
  • Publication number: 20250121486
    Abstract: A toolbox handle structure includes a chamber and a tool slot, and includes an opening on one end. A receiving tube is movably arranged in the chamber. An inner sleeve is inserted in the receiving tube. A bead-holding recess and a hole are disposed on one side adjacent to the opening. A pressing spring is disposed in the inner sleeve to abut against the pressing set. A bead is disposed in the bead-holding recess and pushed by the pressing set to protrude from the hole and abuts the receiving tube. A pressing set is moved by an external force to make the bead fall into the bead-holding recess to be released from abutting against the receiving tube.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 17, 2025
    Inventor: Wei-Cheng CHEN
  • Patent number: 12276906
    Abstract: Methods for removing haze defects from a photomask or reticle are disclosed. The photomask is placed into a chamber which includes a hydrogen atmosphere. The photomask is then exposed to radiation. The energy from the radiation, together with the hydrogen, causes decomposition of the haze defects. The methods can be practiced on-site and quickly, without the need for wet chemicals or the need to remove the pellicle before cleaning of the photomask. A device for conducting the methods is also disclosed herein.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: April 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Hsiung Huang, Yung-Cheng Chen, Chi-Lun Lu
  • Publication number: 20250119945
    Abstract: This disclosure describes systems, methods, and devices related to peer-to-peer (P2P) Wi-Fi sensing. A device may generate a request to perform P2P Wi-Fi sensing operations with a second non-AP STA; send the request to an AP to which the non-AP STA is associated; identify a response received from the AP, the response indicating that the non-AP STA is a sensing receiver for the P2P Wi-Fi sensing operations; identify a trigger frame received from the AP, the trigger frame associated with the P2P Wi-Fi sensing operations; identify a sensing physical layer (PHY) protocol data unit (PPDU) received from the second non-AP STA, the sensing PPDU associated with the P2P Wi-Fi sensing operations and including an indication that the second non-AP STA sent the sensing PPDU; and determine channel state information based on the sensing PPDU, the channel state information indicative of motion of people or objects.
    Type: Application
    Filed: November 18, 2024
    Publication date: April 10, 2025
    Inventors: Cheng CHEN, Bahareh SADEGHI, Claudio DA SILVA, Carlos CORDEIRO
  • Publication number: 20250118690
    Abstract: A semiconductor package includes: a die having a conductive pad at a first side of the die; and a redistribution structure over the first side of the die and electrically coupled to the die. The redistribution structure includes: a first dielectric layer including a first dielectric material; a first via in the first dielectric layer, where the first via is electrically coupled to the conductive pad of the die; and a first dielectric structure embedded in the first dielectric layer, where the first dielectric structure includes a second dielectric material different from the first dielectric material, where the first dielectric structure laterally surrounds the first via and contacts sidewalls of the first via.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: Wen-Yi Lin, Kan-Ju Yang, Kai-Cheng Chen, Chien-Li Kuo, Chien-Chen Li
  • Publication number: 20250120167
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu