Abstract: An analog-to-digital converter (ADC) circuit including a receiving circuit and a delta-sigma ADC is provided. The receiving circuit receives a first analog input and a second analog input, and uses the first or second analog input as an output signal according to a control signal. The delta-sigma ADC converts the output signal to input data. The delta-sigma ADC over-samples the input data to generate a plurality of sampling results and stores the sampling results. The delta-sigma ADC generates output data according to the sampling results.

Abstract: A processing circuit including a first oscillation circuit, a second oscillation circuit, a counting circuit, and a control circuit is provided. The first oscillation circuit receives an input voltage and generates a first clock signal according to the input voltage. The second oscillation circuit receives an output voltage and generates a second clock signal according to the output voltage. The counting circuit receives the output voltage. The counting circuit adjusts a first counter value according to the first clock signal and adjusts a second counter value according to the second clock signal. The control circuit receives the output voltage and determines whether the input voltage is experiencing an attack according to the first counter value and the second counter value. The first oscillation circuit operates in an un-protected power domain. The second oscillation circuit, the counting circuit, and the control circuit operate in a protected power domain.

Abstract: A comparator testing circuit and a testing method are provided. The comparator testing circuit includes a switching circuit, a comparator, and a determination circuit. The switching circuit receives a first signal, a second signal, and a switching signal, and outputs one of the first signal and the second signal as a first input signal and the other of the first signal and the second signal as a second input signal according to the switching signal. The comparator compares the first input signal with the second input signal to generate an output signal. The determination circuit determines whether the comparator is abnormal based on the switching signal and the output signal to generate an exception flag.

Abstract: A management controller is coupled to a plurality of external devices. The management controller includes a control circuit and a transmission circuit. The control circuit generates a control signal according to a first counting value and a second counting value. The transmission circuit is coupled to the external devices. In response to the first counting value not being equal to a first target value, the transmission circuit enters a circulating mode according to the control signal. In the circulating mode, the transmission circuit triggers the external devices in order. In response to the second counting value not being equal to a second target value, the transmission circuit continues to operate in the circulating mode. In response to the second counting value being equal to the second target value, the transmission circuit exits the circulating mode.

Abstract: An electronic device including a power supply device and a load is provided. The power supply device includes an energy harvest circuit, a power management circuit, and an energy storage element. The energy harvest circuit receives a wireless signal and harvests energy from the wireless signal to generate a first output voltage. The power management circuit processes the first output voltage to generate a second output voltage. The energy storage element is charged by the second output voltage to provide an operation voltage. The load operates according to the operation voltage.

Abstract: A detection circuit for detecting a clock signal includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer outputs either a first signal or a second signal as a selection signal. The digital-to-analog converter outputs a reference voltage according to the selection signal. The comparator compares the clock signal to the reference voltage to generate a comparison signal. The counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal. The overflow signal indicates the amplitude of the clock signal.

Abstract: A detection circuit for detecting a clock signal includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer outputs either a first signal or a second signal as a selection signal. The digital-to-analog converter outputs a reference voltage according to the selection signal. The comparator compares the clock signal to the reference voltage to generate a comparison signal. The counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal. The overflow signal indicates the amplitude of the clock signal.

Abstract: A programmable serial input-output controller is provided. A timer circuit performs a timing operation. An input pin is configured to receive an input signal from an external circuit. An output pin is configured to provide an output signal to the external circuit. In an output mode, the sequence controller provides an initial level to the output pin and controls the timer circuit to perform the timing operation. In response to a duration of the timer circuit performing the timing operation reaching first transmission time, the sequence controller inverts the level of the output pin and controls the timer circuit to re-perform the timing operation. In response to the duration of the timer circuit re-performing the timing operation reaching second transmission time, the sequence controller inverts the level of the output pin.

Abstract: A control circuit is provided. A first input-output pin is coupled to a display device and a capacitive touch device. A second input-output pin is coupled to the display device and a capacitive touch device. A sensing circuit determines whether the capacitive touch device is touched according to the voltages of the first and second input-output pins. A display controller provides a first driving signal to the display device via the first input-output pin and provides a second driving signal to the display device via the second input-output pin in a first display period and a second display period. From the end time point of the first display period to the start time point of the second display period, the sensing circuit detects the voltage level of the first input-output pin and stops detecting the voltage of the second input-output pin.

Abstract: A control circuit including a first input-output pin, a second input-output pin, a sensing circuit and a display controller is provided. The first input-output pin is configured to be coupled to a first input pin of a display device and a first sensing pin of a capacitive touch device. The second input-output pin is configured to be coupled to a second input pin of the display device and a second sensing pin of the capacitive touch device. The display controller provides a first driving signal to the display device via the first input-output pin and providing a second driving signal to the display device via the second input-output pin in a display period. In a first sensing period, the voltage level of the first input-output pin is equal to a first predetermined level, and the sensing circuit detects the voltage of the second input-output pin.

Abstract: An encryption and decryption system includes a first electronic device and a second electronic device. The first electronic device includes a memory device and an encryption device. The memory device can store plaintext data. The encryption device can generate first pseudo data and first pseudo key. The encryption device encrypts first pseudo data by the first pseudo key and encrypt the plaintext data by a key, and outputs the ciphertext data generated by encrypting plaintext data by the key. The second electronic device includes a decryption device for generating second pseudo data and the second pseudo key. The decryption device decrypts the second pseudo data by the second pseudo key, and decrypts the ciphertext data by the key, and outputs the plaintext data, which is generated by decrypting the ciphertext data by the key.

Abstract: A control circuit is provided. A memory is configured to store a program code. A central processing unit (CPU) executes a plurality of instructions according to the program code. When a specific instruction is executed by the CPU, the CPU generates a control signal. A power mode management circuit generates a selection signal according to the control signal. A processing circuit transforms first power data according to the selection signal. A first storage circuit stores the first power data. The processing circuit generates first set data and second set data according to first power data. A first specific device operates in a first power mode according to the first set data. A second specific device operates in a second power mode according to the second set data. The first storage circuit, the power mode management circuit and the processing circuit are in an always-on state.

Abstract: A programmable serial input-output controller is provided. A timer circuit performs a timing operation. An input pin is configured to receive an input signal from an external circuit. An output pin is configured to provide an output signal to the external circuit. In an output mode, the sequence controller provides an initial level to the output pin and controls the timer circuit to perform the timing operation. In response to a duration of the timer circuit performing the timing operation reaching first transmission time, the sequence controller inverts the level of the output pin and controls the timer circuit to re-perform the timing operation. In response to the duration of the timer circuit re-performing the timing operation reaching second transmission time, the sequence controller inverts the level of the output pin.

Abstract: A management controller is coupled to a plurality of external devices. The management controller includes a control circuit and a transmission circuit. The control circuit generates a control signal according to a first counting value and a second counting value. The transmission circuit is coupled to the external devices. In response to the first counting value not being equal to a first target value, the transmission circuit enters a circulating mode according to the control signal. In the circulating mode, the transmission circuit triggers the external devices in order. In response to the second counting value not being equal to a second target value, the transmission circuit continues to operate in the circulating mode. In response to the second counting value being equal to the second target value, the transmission circuit exits the circulating mode.

Abstract: A waveform generator is provided. The waveform generator includes a timer and a digital to analog converter (DAC). The timer periodically provides a trigger signal according to a fixed time period. In response to the trigger signal, the DAC is configured to convert first digital data into output voltage of an analog signal. A data hold register is configured to store second digital data that corresponds to the previous output voltage of the analog signal. A judgment circuit is configured to provide a first control signal according to the second digital data, and the first control signal indicates that the previous output voltage is within a first voltage range. A calculation circuit is configured to obtain the first digital data according to the second control signal, the second digital data, and a voltage variation that corresponds to the first voltage range and to update the second digital data.

Abstract: A processing circuit including a first oscillation circuit, a second oscillation circuit, a counting circuit, and a control circuit is provided. The first oscillation circuit receives an input voltage and generates a first clock signal according to the input voltage. The second oscillation circuit receives an output voltage and generates a second clock signal according to the output voltage. The counting circuit receives the output voltage. The counting circuit adjusts a first counter value according to the first clock signal and adjusts a second counter value according to the second clock signal. The control circuit receives the output voltage and determines whether the input voltage is experiencing an attack according to the first counter value and the second counter value. The first oscillation circuit operates in an un-protected power domain. The second oscillation circuit, the counting circuit, and the control circuit operate in a protected power domain.

Abstract: A control device for adjusting the output voltage of a voltage generator, wherein the control device includes a master circuit, a slave circuit, and a power-scaling control circuit, is provided. The master circuit is coupled to a system bus. The slave circuit is coupled to the system bus. The power-scaling control circuit is coupled between the master circuit and the slave circuit. In response to the master circuit sending a voltage-scaling command, the power-scaling control circuit sets a control signal at a suspension level so that the slave circuit sets a specific signal transmitted by the system bus at a wait level. In response to the specific signal being at the wait level, the master circuit stops accessing the first specific device of the slave circuit. In response to the control signal being at the suspension level, the power-scaling control circuit adjusts the output voltage.

Abstract: A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.

Abstract: A driving protection circuit is coupled to a load via an input/output pin. A signal generator circuit is configured to generate a driving signal. An input/output circuit transmits the driving signal to the input/output pin according to an enable signal. A counter circuit adjusts the count value when the enable signal is at a predetermined level. A detection circuit detects the voltage level of the input/output pin to generate a detection signal. When the count value is equal to a predetermined value, a control circuit determines whether the level of the detection signal is the same as the level of the driving signal. When the level of the detection signal is not the same as the level of the driving signal, the control circuit sends an error signal to turn off power to the load.

Abstract: A data processing system includes a memory device, a predetermined voltage generating circuit and a reference voltage generating circuit. The memory device stores system data and operates based on a system high voltage. The predetermined voltage generating circuit is coupled to the memory device and generates a predetermined voltage having a target voltage level according to a reference voltage. The target voltage level is the voltage level required for performing a write operation or an erase operation of the memory device. The reference voltage generating circuit generates the reference voltage. A voltage generator of the reference voltage generating circuit is enabled or disabled in response to a write protection signal, so as to selectively output the reference voltage. When the voltage generator is disabled, the reference voltage will not be output and the predetermined voltage having a target voltage level will accordingly not be generated.