Abstract: A memory circuit and a testing method thereof are provided. The memory circuit includes multiple stage non-volatile memory (NVM) devices. An Nth stage NVM device includes a logic memory circuit, an NVM element, a write circuit and a read circuit. The logic memory circuit receives external data via a data input terminal in a normal mode and receives test data via a test input terminal in a test mode. The write circuit writes the test data or the external data to the NVM element during a writing period. The read circuit transmits stored data stored in the NVM element to an output terminal of the logic memory circuit during a reading period.

Abstract: A system on chip (SOC) is provided. The SOC includes a system core logic, a voltage regulator, a clock generator and a system balance circuit. The voltage regulator provides an operating voltage to the system core logic and receives a current setting signal to set the voltage regulator to a low current mode or a high current mode. The clock generator provides a reference clock signal. The system balance circuit receives the reference clock signal to provide the current setting signal to the voltage regulator and provides the system clock signal to the system core logic, wherein the current setting signal is used to set the voltage regulator to the high current mode before the system clock signal is enabled, and set the voltage regulator to the low current mode after the system clock signal is enabled.

Abstract: A power circuit and a memory device using the same are provided. The power circuit is used for providing an operating voltage to a memory array, and includes a voltage regulator circuit and a voltage feedback circuit. The voltage regulator circuit receives a system voltage to provide the operating voltage. The voltage feedback circuit is coupled to the voltage regulator circuit to receive the operating voltage, and receives a data locking voltage, wherein the voltage feedback circuit has a non-volatile memory element which is set or reset in response to the data locking voltage. The voltage feedback circuit is set or reset based on the non-volatile memory element to provide a feedback voltage to the voltage regulator circuit, so as to set an output level of the operating voltage.

Abstract: A control device and a power conversion circuit thereof are provided. The control device includes a first switch, a second switch, a switching circuit, a first circuit and a second circuit. The control device is selectively switched to a first mode or a second mode corresponding to an operating current and an operating state of a predetermined circuit. During the first mode, an output signal of the first circuit is transmitted to a control end of the first switch through the switching circuit, and the first circuit and the first switch form a low drop-out regulator. During the second mode, a plurality of driving signals of the second circuit are transmitted to the control end of the first switch and a control end of the second switch through the switching circuit, and the first switch, the second switch and an impedance circuit form a switching voltage converter.

Abstract: A fluid flow metering device and a method thereof are provided. The fluid flow metering device includes a fluid flow detector, a memory, a micro controller and a power generator. The fluid flow detector is disposed in a supply tube of a fluid flow provider. When the fluid flows in the supply tube, the power generator generates a supplying power through flow of the fluid, and provides the supplying power to the fluid flow detector, the memory and the micro controller. When the fluid flow detector detects the flow of the fluid, the fluid flow detector detects the flow of the fluid outputted from the supply tube to derive a detecting value. The micro controller receives the detecting value and writes the detecting value into the memory, or the micro controller converts the detecting value into a flow value and writes the flow value into the memory.

Abstract: A sensing device includes a comparator, a first and a second variable capacitor units. The first and second variable capacitor units charge a first and a second comparator inputs, respectively, according to a first and a second driving signals, such that the first and second comparator inputs have a first and a second voltages, respectively, in which a voltage level of the first driving signal is higher than a voltage level of the second driving signal. The comparator is configured to compare the first voltage and the second voltage to generate a comparator output signal. The first variable capacitor unit is adjusted according to the comparator output signal to perform potential compensation for the first comparator input, or the second variable capacitor unit is adjusted according to the comparator output signal to perform potential compensation for the second comparator input.

Abstract: A power circuit and a memory device using the same are provided. The power circuit is used for providing an operating voltage to a memory array, and includes a voltage regulator circuit and a voltage feedback circuit. The voltage regulator circuit receives a system voltage to provide the operating voltage. The voltage feedback circuit is coupled to the voltage regulator circuit to receive the operating voltage, and receives a data locking voltage, wherein the voltage feedback circuit has a non-volatile memory element which is set or reset in response to the data locking voltage. The voltage feedback circuit is set or reset based on the non-volatile memory element to provide a feedback voltage to the voltage regulator circuit, so as to set an output level of the operating voltage.

Abstract: A non-volatile memory (NVM) device includes a logic memory circuit, a NVM element, a writing circuit and a reading circuit. The input terminal of the writing circuit and the output terminal of the reading circuit are coupled to the output terminal of the logic memory circuit. The first output terminal of the writing circuit and the first input terminal of the reading circuit are coupled to the first terminal of the NVM element. The second output terminal of the writing circuit and the second input terminal of the reading circuit are coupled to the second terminal of the NVM element. During a writing period, the writing circuit writes the stored data of the logic memory circuit into the NVM element. During a reading period, the reading circuit restores the data of the NVM element to the output terminal of the logic memory circuit.

Abstract: A counting device and a pedometer device is described. The counting device includes: a piezoelectric sensor generating a voltage signal when pressed; a rectifier receiving the voltage signal and rectifying the voltage signal to produce a trigger signal; a non-volatile counter receiving the trigger signal, and including a plurality of non-volatile D flip-flops counting according to the trigger signal and storing count data; a processing module reading the count data and using the count data to generate a counting value; and a wireless communication module transmitting the counting value to an external device. The counting device is powered with electrical energy of the voltage signal generated by the piezoelectric sensor.

Abstract: A sensing device includes a comparator, a first and a second variable capacitor unit. A first comparator input of the comparator is electrically coupled to a touch pad. The first variable capacitor unit is configured to charge the first comparator input such that the first comparator input has a first potential. The second variable capacitor unit is configured to charge a second comparator input of the comparator such that the second comparator input has a second potential. The comparator is configured for comparing the first potential and the second potential to generate a comparator output signal. In a condition of the touch pad being operated, the first variable capacitor unit is adjusted according to the comparator output signal to perform potential compensation for the first comparator input, or the second variable capacitor unit is adjusted according to the comparator output signal to perform potential compensation for the second comparator input.

Abstract: A sensing device includes a comparator, a first switch, a second switch, and a controller. The comparator includes a first input end and a second input end. An end of the first switch is connected to one of a first touch electrode and a second touch electrode that are complementary. An end of the second switch is selectively connected to the second touch electrode. When the first touch electrode and the second touch electrode are touched, the controller controls the first switch to connect the first input end and the first touch electrode, controls the second switch to connect the second input end and the second touch electrode, and calculates a first touch position of the first touch electrode and the second touch electrode.

Abstract: An input/output (I/O) buffer circuit includes an I/O unit, a first register and a second register. The I/O unit selectively transmits digital signals and analog signals according to a first enable signal, and selectively receives signals and outputs signals at an I/O terminal according to a second enable signal. The first register latches a first control signal received before power is turned off, and outputs the first enable signal corresponding to the first control signal to the I/O unit when power is turned on. The second register latches a second control signal received before power is turned off, and outputs the second enable signal corresponding to the second control signal to the I/O unit when power is turned on.

Abstract: A communication device, a communication system and an operation method thereof are provided. The communication device includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is configured to execute a first communication protocol to work with the MCU so as to communicate with another communication device in a first period, and meanwhile the FPGA is programmed with a second communication protocol by the MCU in the same first period. The FPGA is controlled by a switch pulse output from the MCU to terminate the first period, and switched from the first communication protocol to the second communication protocol, and then executes the second communication protocol to work with the MCU so as to communicate with the another communication device in a second period.

Abstract: An input/output (I/O) buffer circuit includes an I/O unit, a first register and a second register. The I/O unit selectively transmits digital signals and analog signals according to a first enable signal, and selectively receives signals and outputs signals at an I/O terminal according to a second enable signal. The first register latches a first control signal received before power is turned off, and outputs the first enable signal corresponding to the first control signal to the I/O unit when power is turned on. The second register latches a second control signal received before power is turned off, and outputs the second enable signal corresponding to the second control signal to the I/O unit when power is turned on.

Abstract: A non-volatile memory (NVM) device includes a logic memory circuit, a NVM element, a writing circuit and a reading circuit. The input terminal of the writing circuit and the output terminal of the reading circuit are coupled to the output terminal of the logic memory circuit. The first output terminal of the writing circuit and the first input terminal of the reading circuit are coupled to the first terminal of the NVM element. The second output terminal of the writing circuit and the second input terminal of the reading circuit are coupled to the second terminal of the NVM element. During a writing period, the writing circuit writes the stored data of the logic memory circuit into the NVM element. During a reading period, the reading circuit restores the data of the NVM element to the output terminal of the logic memory circuit.

Abstract: A function programmable circuit and an operation method thereof are provided. The function programmable circuit includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is capable of being configured to execute a first function and work with the MCU in a first period, while the FPGA is being programmed a second function by the MCU in the same first period. The FPGA is controlled by a function switch pulse output from the MCU to terminate the first period, and switched from the first function to the second function, and then executes the second function and works with the MCU in a second period.

Abstract: An integrated circuit and an operation method thereof are provided. The integrated circuit includes a voltage detecting unit, a central processing unit, a memory unit and a control unit. The voltage detecting unit detects a system voltage and correspondingly outputs a voltage state signal. The central processing unit has at least one register. When the system voltage is downed to a voltage level lower than or equal to a brown-out voltage and greater than a reset low voltage, the control unit stores values of the registers into the memory unit.

Abstract: A function programmable circuit and an operation method thereof are provided. The function programmable circuit includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is capable of being configured to execute a first function and work with the MCU in a first period, while the FPGA is being programmed a second function by the MCU in the same first period. The FPGA is controlled by a function switch pulse output from the MCU to terminate the first period, and switched from the first function to the second function, and then executes the second function and works with the MCU in a second period.

Abstract: A voltage generator and an oscillation device, and an operation method thereof are disclosed. The oscillation device includes a non-volatile memory, the voltage generator and a voltage-controlled oscillation (VCO) circuit. The voltage generator includes a current source. The current source provides a current flowing through the at least one non-volatile memory. The voltage generator uses the non-volatile resistance of the non-volatile memory to generate a bias voltage. The VCO circuit is coupled to the voltage generator so as to generate a corresponding oscillation frequency based on the bias voltage.

Abstract: An input/output (I/O) buffer circuit includes an I/O unit and a protection circuit. The I/O unit selectively receives and outputs signals based on an enable signal. The protection circuit generates a logic control signal to deactivate the I/O unit in a state where a voltage level of the I/O terminal is abnormal. The protection circuit includes a register. The register latches a logic signal corresponding to the voltage level of the I/O terminal in a state where the voltage level of the I/O terminal is abnormal, outputs the logic control signal based on the logic signal, and is preset to output the logic control signal based on the logic signal when a power-off state resumes to a power-on state.