Abstract: A control circuit is provided. A first input-output pin is coupled to a display device and a capacitive touch device. A second input-output pin is coupled to the display device and a capacitive touch device. A sensing circuit determines whether the capacitive touch device is touched according to the voltages of the first and second input-output pins. A display controller provides a first driving signal to the display device via the first input-output pin and provides a second driving signal to the display device via the second input-output pin in a first display period and a second display period. From the end time point of the first display period to the start time point of the second display period, the sensing circuit detects the voltage level of the first input-output pin and stops detecting the voltage of the second input-output pin.

Abstract: A waveform generator is provided. The waveform generator includes a timer and a digital to analog converter (DAC). The timer periodically provides a trigger signal according to a fixed time period. In response to the trigger signal, the DAC is configured to convert first digital data into output voltage of an analog signal. A data hold register is configured to store second digital data that corresponds to the previous output voltage of the analog signal. A judgment circuit is configured to provide a first control signal according to the second digital data, and the first control signal indicates that the previous output voltage is within a first voltage range. A calculation circuit is configured to obtain the first digital data according to the second control signal, the second digital data, and a voltage variation that corresponds to the first voltage range and to update the second digital data.

Abstract: A control circuit including a first input-output pin, a second input-output pin, a sensing circuit and a display controller is provided. The first input-output pin is configured to be coupled to a first input pin of a display device and a first sensing pin of a capacitive touch device. The second input-output pin is configured to be coupled to a second input pin of the display device and a second sensing pin of the capacitive touch device. The display controller provides a first driving signal to the display device via the first input-output pin and providing a second driving signal to the display device via the second input-output pin in a display period. In a first sensing period, the voltage level of the first input-output pin is equal to a first predetermined level, and the sensing circuit detects the voltage of the second input-output pin.

Abstract: A control circuit including an input-output pin, an image driver, a sensing circuit, a first path, a second path and a microcontroller circuit is provided. The input-output pin is configured to be coupled to the first pin of a display device and the second pin of a capacitive touch device. The image driver is configured to provide a driving signal. The sensing circuit determines whether the capacitive touch device is touched according to the voltage of the second pin. The microcontroller circuit turns on the first path and turns off the second path to transmit the driving signal to the display device via the input-output pin in a first operation period. The microcontroller circuit turns on the second path and turns off the first path to transmit the voltage of the second pin to the sensing circuit via the input-output pin in a second operation period.

Abstract: A control circuit including an input-output pin, an image driver, a sensing circuit, a first path, a second path and a microcontroller circuit is provided. The input-output pin is configured to be coupled to the first pin of a display device and the second pin of a capacitive touch device. The image driver is configured to provide a driving signal. The sensing circuit determines whether the capacitive touch device is touched according to the voltage of the second pin. The microcontroller circuit turns on the first path and turns off the second path to transmit the driving signal to the display device via the input-output pin in a first operation period. The microcontroller circuit turns on the second path and turns off the first path to transmit the voltage of the second pin to the sensing circuit via the input-output pin in a second operation period.

Abstract: A control device for adjusting the output voltage of a voltage generator, wherein the control device includes a master circuit, a slave circuit, and a power-scaling control circuit, is provided. The master circuit is coupled to a system bus. The slave circuit is coupled to the system bus. The power-scaling control circuit is coupled between the master circuit and the slave circuit. In response to the master circuit sending a voltage-scaling command, the power-scaling control circuit sets a control signal at a suspension level so that the slave circuit sets a specific signal transmitted by the system bus at a wait level. In response to the specific signal being at the wait level, the master circuit stops accessing the first specific device of the slave circuit. In response to the control signal being at the suspension level, the power-scaling control circuit adjusts the output voltage.

Abstract: A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.

Abstract: A clock glitch detection circuit includes a detection circuit and a logic circuit. The detection circuit is configured to receive a clock input signal and a clock output signal and determines whether the clock input signal and the clock output signal are in phase, so as to output a first detection signal and a second detection signal. The logic circuit is coupled to the detection circuit and configured to receive the first detection signal and the second detection signal. The logic circuit determines whether the first detection signal and the second detection signal are in phase, so as to generate a glitch detection signal. The glitch detection signal is configured to indicate whether clock glitch occurs in the clock input signal.

Abstract: A data processing system includes a memory device, a predetermined voltage generating circuit and a reference voltage generating circuit. The memory device stores system data and operates based on a system high voltage. The predetermined voltage generating circuit is coupled to the memory device and generates a predetermined voltage having a target voltage level according to a reference voltage. The target voltage level is the voltage level required for performing a write operation or an erase operation of the memory device. The reference voltage generating circuit generates the reference voltage. A voltage generator of the reference voltage generating circuit is enabled or disabled in response to a write protection signal, so as to selectively output the reference voltage. When the voltage generator is disabled, the reference voltage will not be output and the predetermined voltage having a target voltage level will accordingly not be generated.

Abstract: A control circuit is provided. A memory is configured to store a program code. A central processing unit (CPU) executes a plurality of instructions according to the program code. When a specific instruction is executed by the CPU, the CPU generates a control signal. A power mode management circuit generates a selection signal according to the control signal. A processing circuit transforms first power data according to the selection signal. A first storage circuit stores the first power data. The processing circuit generates first set data and second set data according to first power data. A first specific device operates in a first power mode according to the first set data. A second specific device operates in a second power mode according to the second set data. The first storage circuit, the power mode management circuit and the processing circuit are in an always-on state.

Abstract: An encryption and decryption system includes a first electronic device and a second electronic device. The first electronic device includes a memory device and an encryption device. The memory device can store plaintext data. The encryption device can generate first pseudo data and first pseudo key. The encryption device encrypts first pseudo data by the first pseudo key and encrypt the plaintext data by a key, and outputs the ciphertext data generated by encrypting plaintext data by the key. The second electronic device includes a decryption device for generating second pseudo data and the second pseudo key. The decryption device decrypts the second pseudo data by the second pseudo key, and decrypts the ciphertext data by the key, and outputs the plaintext data, which is generated by decrypting the ciphertext data by the key.

Abstract: A memory circuit and a testing method thereof are provided. The memory circuit includes multiple stage non-volatile memory (NVM) devices. An Nth stage NVM device includes a logic memory circuit, an NVM element, a write circuit and a read circuit. The logic memory circuit receives external data via a data input terminal in a normal mode and receives test data via a test input terminal in a test mode. The write circuit writes the test data or the external data to the NVM element during a writing period. The read circuit transmits stored data stored in the NVM element to an output terminal of the logic memory circuit during a reading period.

Abstract: A driving protection circuit is coupled to a load via an input/output pin. A signal generator circuit is configured to generate a driving signal. An input/output circuit transmits the driving signal to the input/output pin according to an enable signal. A counter circuit adjusts the count value when the enable signal is at a predetermined level. A detection circuit detects the voltage level of the input/output pin to generate a detection signal. When the count value is equal to a predetermined value, a control circuit determines whether the level of the detection signal is the same as the level of the driving signal. When the level of the detection signal is not the same as the level of the driving signal, the control circuit sends an error signal to turn off power to the load.

Abstract: A programmable array logic includes a plurality of first signal lines, a plurality of second signal lines coupled to input terminals of a plurality of programmable AND gates, a plurality of first control units coupled to the first signal lines and second signal lines, a plurality of third signal lines coupled to output terminals of the programmable AND gates, a plurality of fourth signal lines coupled to input terminals of a plurality of programmable OR gates, and a plurality of second control units coupled to the third signal lines and the fourth signal lines. Each of the first control units has at least a first resistive memory for setting voltage level relationship between the first signal lines and the second signal lines. Each of second control units has a second resistive memory for setting voltage level relationship between the third signal lines and the fourth signal lines.

Abstract: A control device includes a first switch, a second switch, a switching circuit, a first circuit and a second circuit. The control device is selectively switched to a first mode or a second mode corresponding to an operating current and an operating state of a predetermined circuit. During the first mode, an output signal of the first circuit is transmitted to a control end of the first switch through the switching circuit, and the first circuit and the first switch form a low drop-out regulator. During the second mode, a plurality of driving signals of the second circuit are transmitted to the control end of the first switch and a control end of the second switch through the switching circuit, and the first switch, the second switch and an impedance circuit form a switching voltage converter.

Abstract: An input/output (I/O) buffer circuit includes an I/O unit and a protection circuit. The I/O unit selectively receives and outputs signals based on an enable signal. The protection circuit generates a logic control signal to deactivate the I/O unit in a state where a voltage level of the I/O terminal is abnormal. The protection circuit includes a register. The register latches a logic signal corresponding to the voltage level of the I/O terminal in a state where the voltage level of the I/O terminal is abnormal, outputs the logic control signal based on the logic signal, and is preset to output the logic control signal based on the logic signal when a power-off state resumes to a power-on state.

Abstract: A programmable array logic includes a plurality of first signal lines, a plurality of second signal lines coupled to input terminals of a plurality of programmable AND gates, a plurality of first control units coupled to the first signal lines and second signal lines, a plurality of third signal lines coupled to output terminals of the programmable AND gates, a plurality of fourth signal lines coupled to input terminals of a plurality of programmable OR gates, and a plurality of second control units coupled to the third signal lines and the fourth signal lines. Each of the first control units has at least a first resistive memory for setting voltage level relationship between the first signal lines and the second signal lines. Each of second control units has a second resistive memory for setting voltage level relationship between the third signal lines and the fourth signal lines.

Abstract: A system on chip (SOC) is provided. The SOC includes a system core logic, a voltage regulator, a clock generator and a system balance circuit. The voltage regulator provides an operating voltage to the system core logic and receives a current setting signal to set the voltage regulator to a low current mode or a high current mode. The clock generator provides a reference clock signal. The system balance circuit receives the reference clock signal to provide the current setting signal to the voltage regulator and provides the system clock signal to the system core logic, wherein the current setting signal is used to set the voltage regulator to the high current mode before the system clock signal is enabled, and set the voltage regulator to the low current mode after the system clock signal is enabled.

Abstract: A communication device, a communication system and an operation method thereof are provided. The communication device includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is configured to execute a first communication protocol to work with the MCU so as to communicate with another communication device in a first period, and meanwhile the FPGA is programmed with a second communication protocol by the MCU in the same first period. The FPGA is controlled by a switch pulse output from the MCU to terminate the first period, and switched from the first communication protocol to the second communication protocol, and then executes the second communication protocol to work with the MCU so as to communicate with the another communication device in a second period.

Abstract: A counting device and a pedometer device is described. The counting device includes: a piezoelectric sensor generating a voltage signal when pressed; a rectifier receiving the voltage signal and rectifying the voltage signal to produce a trigger signal; a non-volatile counter receiving the trigger signal, and including a plurality of non-volatile D flip-flops counting according to the trigger signal and storing count data; a processing module reading the count data and using the count data to generate a counting value; and a wireless communication module transmitting the counting value to an external device. The counting device is powered with electrical energy of the voltage signal generated by the piezoelectric sensor.