Abstract: A computer system power-on security control that does not allow a computer power source to turn on until a valid passcode is entered. The system includes a mouse intercept unit for intercepting mouse signals directed to a mouse controller in the computer system when the power source is off. A memory stores valid passcodes used to power on the computer system. A comparator unit is configured to compare received mouse signals to the stored passcodes. A power supply control unit, connected to the comparator unit, outputs a power control signal to turn on the computer system power source when the mouse signals match the stored passcode.

Abstract: A controller circuit and a method to wake up or turn on a computer system by a peripheral device comprising a MIDI port. When the computer system is in a standby or an off state, a certain value or combination of the peripheral device is preset as a default value. Inputting a certain signal to the peripheral device, the wake up/turn on function can be achieved.

Abstract: An operation mode for waking up a system predetermined by a user is stored before the system is in standby mode. After the system is in standby mode, the peripherals and the peripheral controller are separated to prevent the peripheral controller from receiving the output signal from the peripherals. The wake-up control circuit then receives the output signal from the peripherals. In the standby mode, if the output signal from the peripherals is consistent with the user's predetermined operation mode, the system is woken up by the wake-up control circuit and returns to the normal operation mode.

Abstract: A solution for maintaining the wake-up functions of a computer after a power loss is provided. To reset parameters relating to the wake-up functions, the computer is automatically turned on when the power is supplied again. Then, the computer is forced to be power-off by an output signal to switch the computer system to a state capable of executing the wake-up functions.

Abstract: A computer system power-on security control apparatus is described to provide shielding against unauthorized access to the computer systems. Firmware-level protection is provided instead of the conventional implementation at the operating system level. Repeated power-on and -off cycles inevitable in the process of trial entry of the password of the computer system can be avoided altogether, reducing the risk of potential damages to delicate subsystems in the computer while repeated trial of the password is attempted.

Abstract: A LPC/ISA bridge and its bridging method are disclosed for bridging an LPC interface to an ISA interface. The LPC/ISA bridge is activated in response to a duty cycle indicative signal (LFRAME#), and serially transforms related command, address and data information from command/address/data lines (LAD[3:0]) of the LPC interface into address, data and control signals of the ISA interface. Therefore, the problem as to the interface incompatibility is solved.

Abstract: A computer starter and starting method for an ATX computer system which provides a standby voltage when the computer system is shut down. The computer starter takes the standby signal as its power supply and includes a smart card interface, a clock generator, a non-volatile memory, a micro-controller and a power control circuit. The smart card interface generates an enable signal upon insertion of a smart card. The clock generator generates a reference clock in response to the enable signal. The non-volatile memory stores a computer identification signal. The micro-controller resets the smart card, reads a user identification signal stored in the smart card, and generates a verification signal when the computer identification signal stored in the non-volatile memory matches the user identification signal stored in the smart card. The power control circuit generates a start signal in response to the verification signal so as to start the computer system.

Abstract: A computer system power-on security control apparatus is disclosed to provide shielding against unauthorized access to the computer systems. Firmware-level protection is provided instead of the conventional implementation at the operating system level. Repeated power-on and -off cycles inevitable in the process of trial entry of the password of the computer system can be avoided altogether, reducing the risk of potential damages to delicate subsystems in the computer while repeated trial of the password is attempted.

Abstract: A power monitoring circuit for monitoring the power being supplied to a central processing unit (CPU) is provided. This power monitoring circuit can adaptively adjust for a suitable power level corresponding to the power rating of the CPU. The CPU on which the power monitoring circuit is used should be of the type having a factory-preset built-in power-rating code that indicates the tolerable power range acceptable by the CPU. The power monitoring circuit includes decoding means that can decode the power-rating code into a bottom-limit reference value and an bottom-limit reference value which indicate respectively the bottom and upper limits of the tolerable power range acceptable by the CPU. Further, the power monitoring circuit includes means for comparing the magnitude of the power being supplied to the CPU against the bottom-limit reference value and the bottom-limit reference value to see if the power is within the tolerable power range acceptable by the CPU.