Patents by Inventor Cheng-Chung Lin
Cheng-Chung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230027552Abstract: A fluid immersion cooling system includes a fluid tank that contains a layer of a dual-phase coolant fluid and one or more layers of single-phase coolant fluids. The dual-phase and single-phase coolant fluids are immiscible, with the dual-phase coolant fluid having a lower boiling point and higher density than a single-phase coolant fluid. A substrate of an electronic system is submerged in the tank such that high heat-generating components are immersed at least in the layer of the dual-phase coolant fluid. Heat from the components is dissipated to the dual-phase coolant fluid to generate vapor bubbles of the dual-phase coolant fluid. The vapor bubbles rise to a layer of a single-phase coolant fluid that is above the layer of the dual-phase coolant fluid. The vapor bubbles condense to droplets of the dual-phase coolant fluid. The droplets fall down into the layer of the dual-phase coolant fluid.Type: ApplicationFiled: July 23, 2021Publication date: January 26, 2023Applicant: Super Micro Computer, Inc.Inventors: Yueh Ming LIU, Yu Hsiang HUANG, Yu Chuan CHANG, Tan Hsin CHANG, Hsiao Chung CHEN, Chia-Wei CHEN, Chih-Ta CHEN, Cheng-Hung LIN, Ming-Te HSU
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Publication number: 20220392906Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.Type: ApplicationFiled: August 9, 2022Publication date: December 8, 2022Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
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Publication number: 20220384269Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Patent number: 11506611Abstract: A surface-enhanced Raman scattering (SERS) detection method is provided for detecting a target analyte in a sample. The SERS detection method generally includes the steps of: (a). preparing an extract of the sample; (b). introducing the sample extract onto a SERS substrate, causing the target analyte to be absorbed in the SERS substrate; (c). introducing a volatile organic solvent onto the SERS substrate to have the target analyte of the sample extract dissolved and comes out of the SERS substrate; (d). irradiating the SERS substrate with light to evaporate the volatile organic solvent, leaving a more condensed target analyte on the SERS substrate; (e). irradiating the condensed target analyte with laser light to have the target analyte penetrate deeply into the SERS substrate; and (f). performing Raman measurement with a laser beam focusing on the SERS substrate to analyze the target analyte.Type: GrantFiled: July 20, 2017Date of Patent: November 22, 2022Assignee: PHANSCO CO., LTD.Inventors: Chao-Ming Tsen, Ching-Wei Yu, Wei-Chung Chao, Yung-Hsiang Wang, Cheng-Chien Li, Shao-Kai Lin, Tzu-Hung Hsu, Chang-Jung Wen
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Patent number: 11499219Abstract: A method of fabricating a thin film with a varying thickness includes the steps of providing a shadow mask with an opening, providing a carrier plate, arranging a substrate on the carrier plate, and coating the substrate through the opening whilst rotating the carrier plate relative to the shadow mask. A plurality of zones of the substrates is swept and exposed from arcuate portions of the opening per each turn by a plurality of predetermined exposure times, respectively. The varying thickness of the thin film corresponds to variation of the predetermined exposure times.Type: GrantFiled: November 10, 2020Date of Patent: November 15, 2022Assignee: National Chiao Tung UniversityInventors: Cheng-Sheng Huang, Chi-Yung Hsieh, Yu-Chi Lin, Chih-Chung Wu, Chi-Fang Huang
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Patent number: 11502076Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: GrantFiled: November 30, 2018Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Publication number: 20220354007Abstract: A method of manufacturing a casing of an electronic device including the following steps is provided. A metallic housing is provided, wherein the metallic housing has an inner surface and an outer surface opposite to the inner surface and includes a back region and at least one side region. At least one gap, a plurality of apertures and a non-conductive layer are formed on the inner surface of the metallic housing, wherein the apertures is formed on a surface of the at least one gap, part of the non-conductive layer is formed in the at least one gap and extended from the back region to the at least one side region, and part of the non-conductive layer is extended into the apertures. Part of the metallic housing is removed for exposing part of the non-conductive layer, thereby forming a plurality of non-conductive spacers located in the at least one gap.Type: ApplicationFiled: July 17, 2022Publication date: November 3, 2022Applicant: HTC CorporationInventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
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Publication number: 20220350235Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.Type: ApplicationFiled: June 30, 2022Publication date: November 3, 2022Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
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Publication number: 20220336739Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
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Publication number: 20220317713Abstract: A power supply system includes an output terminal, a power supply control chip, a power supply switch and a detection device. The power supply control chip is configured to adjust the amount of an input power providing to an electronic device by the power supply device. The power supply switch is configured to control the connection between the power supply device and the power supply control chip. The detection device is configured to detect whether the power supply control chip operates normally. When the power supply control chip operates abnormally, the detection device controls the connection between the power supply device and the power supply control chip through the power supply switch for restarting the power supply control chip. The power supply control chip, the power supply switch and the detection device are disposed in an enclosed space.Type: ApplicationFiled: July 22, 2021Publication date: October 6, 2022Inventors: Shih-Chung Wang, Cheng-Yu Shu, Wei-Chieh Lin
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Patent number: 11457535Abstract: A metallic housing of an electronic device including an inner surface, an outer surface and a first non-conductive spacer is provided. The outer surface is opposite to the inner surface, and the outer surface has a back side and lateral sides connecting with the back side. The inner surface is substantially a recessed structure. The metallic housing having a first gap and a second gap substantially located at two opposite ends of the metallic housing and being parallel with each other. The first gap and the second gap each communicates the inner surface and the outer surface. The first non-conductive spacer is disposed the first gap of the metallic housing.Type: GrantFiled: November 17, 2020Date of Patent: September 27, 2022Assignee: HTC CorporationInventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
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Patent number: 11455528Abstract: The present invention provides an automated optical inspection and classification apparatus based on a deep learning system, comprising a camera and a processor. The processor executes a deep learning system after loading data from a storage unit and the processor, and comprises an input layer, a neural network layer group, and a fully connected-layer group. The neural network layer group is for extracting to an input image and thereby obtaining a plurality of image features. The fully connected-layer group is for performing weight-based classification and outputting an inspection result.Type: GrantFiled: June 27, 2019Date of Patent: September 27, 2022Assignee: UTECHZONE CO., LTD.Inventors: Arulmurugan Ambikapathi, Chien-Chung Lin, Cheng-Hua Hsieh
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Publication number: 20220303309Abstract: The present invention discloses a hacking detection method, including: deploying a plurality of trap IP addresses in a trap IP address list; collecting access logs from a plurality of network devices to create a connection record list, wherein the connection record list includes a plurality of connection records; and comparing the trap IP address list and the connection record list to obtain a suspicious source list. The suspicious source list includes a plurality of suspicious source IP addresses. The suspicious source IP addresses match a portion of the trap IP addresses in the trap IP address list.Type: ApplicationFiled: May 14, 2021Publication date: September 22, 2022Inventors: Chen-Chung LEE, Chia-Hung LIN, Cheng-Yao WANG, Li-Pin TSENG
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Publication number: 20220299717Abstract: A contactless connector includes: a light emitter for emitting light; a light-transmitting member at least partially covering the light emitter; and an alignment mechanism that enables an alignment error between the light emitter and a light receiver on another contactless connector to be not greater than 5 microns; wherein the light-transmitting member includes a mating surface that is matched with an opposite surface of the another contactless connector and there is an elastic member on the opposite surface of the another contactless connector to adjust alignment of the alignment mechanism.Type: ApplicationFiled: March 16, 2022Publication date: September 22, 2022Inventors: TUNG-LOU LIN, CHANG-TENG HSU, HAI-JUN XU, CHENG-HSIU LU, CHAO-CHUNG CHANG
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Publication number: 20220292039Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is coupled to a DP sink device through a DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit supports only one specific conduction mode that only allows transmitting DP signals between the USB interface circuit and the DP interface circuit.Type: ApplicationFiled: May 30, 2022Publication date: September 15, 2022Applicant: VIA LABS, INC.Inventors: Cheng-Chung Lin, Hsiao-Chyi Lin, Yi-Shing Lin, Chien-Sheng Chen
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Publication number: 20220285374Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.Type: ApplicationFiled: May 3, 2021Publication date: September 8, 2022Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
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Patent number: 11430951Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure disposed between a top electrode and a bottom electrode. The data storage structure includes a lower switching layer overlying the bottom electrode, and an upper switching layer overlying the lower switching layer. The lower switching layer comprises a dielectric material doped with a first dopant.Type: GrantFiled: July 27, 2020Date of Patent: August 30, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
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Patent number: 11402743Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.Type: GrantFiled: August 31, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
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Patent number: 11386030Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is suitable for coupling to a DP connector. In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit. The USB core circuit decodes the USB signal pair and generates DP data. The DP data is transmitted to the DP connector by the DP interface circuit. In a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.Type: GrantFiled: December 3, 2020Date of Patent: July 12, 2022Assignee: VIA LABS, INC.Inventors: Cheng-Chung Lin, Hsiao-Chyi Lin, Yi-Shing Lin, Chien-Sheng Chen
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Patent number: 11270052Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.Type: GrantFiled: September 15, 2020Date of Patent: March 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chia Hao Tu, Hsueh-Chih Chou, Sang Hoo Dhong, Jerry Chang Jui Kao, Chi-Lin Liu, Cheng-Chung Lin, Shang-Chih Hsieh