Patents by Inventor Cheng-Chung Lin
Cheng-Chung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160336343Abstract: An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.Type: ApplicationFiled: October 6, 2015Publication date: November 17, 2016Inventors: Ming-Zhang KUO, Ho-Chieh HSIEH, Hui-Zhong ZHUANG, Kuo-Feng TSENG, Lee-Chung LU, Cheng-Chung LIN, Sang Hoo DHONG
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Patent number: 9495495Abstract: One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.Type: GrantFiled: April 3, 2014Date of Patent: November 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Chung Lin, Ming-Zhang Kuo, Sang Hoo Dhong, Ho-Chieh Hsieh, Kuo Feng Tseng
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Publication number: 20160306911Abstract: According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a source side and a drain side; providing a place-and-route boundary (prBoundary) of the first cell based on the configuration of the two sides of the first cell; providing a second cell having two sides, each side configured as at least one of a source side and a drain side; providing a prBoundary of the second cell based on the configuration of the two sides of the second cell; and placing the first cell and the second cell based on the prBoundary of the first cell and the prBoundary of the second cell.Type: ApplicationFiled: April 16, 2015Publication date: October 20, 2016Inventors: MING-ZHANG KUO, LEE-CHUNG LU, CHENG-CHUNG LIN, LI-CHUN TIEN, SANG-HOO DHONG, TA-PEN GUO
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Patent number: 9449931Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.Type: GrantFiled: August 25, 2014Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
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Patent number: 9378926Abstract: An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.Type: GrantFiled: January 23, 2015Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Osamu Takahashi, Sang Hoo Dhong
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Patent number: 9362899Abstract: A clock regenerator includes a pulse generating module, a control logic module, a gating module and an output module. The pulse generating module is configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal. The control logic module is configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals. The gating module is configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal. The output module is configured to provide a local clock signal according to the intermediate clock signal.Type: GrantFiled: December 13, 2013Date of Patent: June 7, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Osamu Takahashi, Sang Hoo Dhong
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Patent number: 9287171Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.Type: GrantFiled: July 28, 2014Date of Patent: March 15, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen Wu, Cheng-Chung Lin, Chien Ling Hwang, Chung-Shi Liu
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Patent number: 9286970Abstract: A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.Type: GrantFiled: July 8, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Zhang Kuo, Cheng-Chung Lin, Ho-Chieh Hsieh, Kuo Feng Tseng, Sang Hoo Dhong
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Patent number: 9281288Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.Type: GrantFiled: February 7, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Lin, Hsiu-Jen Lin, Cheng-Ting Chen, Chun-Cheng Lin, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20160012881Abstract: A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.Type: ApplicationFiled: July 8, 2014Publication date: January 14, 2016Inventors: Ming-Zhang Kuo, Cheng-Chung Lin, Ho-Chieh Hsieh, Kuo Feng Tseng, Sang Hoo Dhong
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Patent number: 9202662Abstract: A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the mirror array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature.Type: GrantFiled: January 31, 2013Date of Patent: December 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jimmy Hsiao, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Osamu Takahashi, Sang Hoo Dhong
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Publication number: 20150286760Abstract: One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.Type: ApplicationFiled: April 3, 2014Publication date: October 8, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Chung Lin, Ming-Zhang Kuo, Sang Hoo Dhong, Ho-Chieh Hsieh, Kuo Feng Tseng
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Publication number: 20150171832Abstract: A clock regenerator includes a pulse generating module, a control logic module, a gating module and an output module. The pulse generating module is configured to receive a global clock signal and produce a periodic pulse signal triggered by a rising edge of the global clock signal. The control logic module is configured to receive a plurality of control signals and produce a pulse-type setting signal and a gating signal according to the periodic pulse signal and the control signals. The gating module is configured to produce an intermediate clock signal according to the pulse-type setting signal and the gating signal. The output module is configured to provide a local clock signal according to the intermediate clock signal.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Zhang KUO, Ping-Lin YANG, Cheng-Chung LIN, Osamu TAKAHASHI, Sang Hoo DHONG
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Publication number: 20150131077Abstract: An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Osamu Takahashi, Sang Hoo Dhong
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Patent number: 8941085Abstract: The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.Type: GrantFiled: June 10, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Osamu Takahashi, Sang Hoo Dhong
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Publication number: 20140363966Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.Type: ApplicationFiled: August 25, 2014Publication date: December 11, 2014Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
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Patent number: 8900922Abstract: A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings.Type: GrantFiled: February 16, 2012Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Lin, Kuei-Wei Huang, Ai-Tee Ang, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu
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Publication number: 20140335687Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.Type: ApplicationFiled: July 28, 2014Publication date: November 13, 2014Inventors: Yi-Wen WU, Cheng-Chung LIN, Chien Ling HWANG, Chung-Shi LIU
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Publication number: 20140268078Abstract: The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.Type: ApplicationFiled: June 10, 2013Publication date: September 18, 2014Inventors: Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Osamu Takahashi, Sang Hoo Dhong
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Patent number: 8823166Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.Type: GrantFiled: August 30, 2010Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu