Abstract: This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material.

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract: A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Abstract: Among other things, one or more techniques for conditional cell placement are provided herein. In an embodiment, a conditional boundary is created for a first cell. For example, the conditional boundary enables the first cell to be placed relative to a second cell based on a conditional placement rule. In an embodiment, the first cell is placed in a first manner relative to the second cell based in a first scenario. In a second scenario, different than the first scenario, the first cell is placed in a second manner relative to the second cell. In this manner, conditional cell placement is provided, thus providing flexibility and improved layout efficiency with regard to semiconductor fabrication, for example.

Abstract: A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings.

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract: A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewalls of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.

Abstract: A picking system comprises a radio frequency identification (RFID) tag, a case, a two-wire conductive strip, at least one identifying unit and a processing unit. The two-wire conductive strip is electrically connected between the identifying unit and the processing unit. The identifying unit reads tag information within the RFID tag for actively and instantly controlling the authorization of an operating staff assigned for particular items thereby improving the accuracy of picking items.

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Abstract: A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump.

Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Abstract: This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material.

Abstract: A power supply circuit for a PCI-E slot includes a control chip, a first electronic switch, and a second electronic switch. The control chip determines a status of a motherboard, outputting a control signal. A first terminal of the first electronic switch is connected to the control chip to receive the control signal, and connected to a +3.3V dual power supply of the motherboard through a first resistor. A second terminal of the first electronic switch is grounded. A third terminal of the first electronic switch is connected to a first terminal of the second electronic switch, and connected to the +3.3V dual power supply through a second resistor. A second terminal of the second electronic switch is connected to the +3.3V dual power supply. A third terminal of the second electronic switch is connected to a PCI-E slot.

Abstract: An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.

Abstract: A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Abstract: A power supply circuit for a PCI-E slot includes a control chip, a first electronic switch, and a second electronic switch. The control chip determines a status of a motherboard, outputting a control signal. A first terminal of the first electronic switch is connected to the control chip to receive the control signal, and connected to a +3.3V dual power supply of the motherboard through a first resistor. A second terminal of the first electronic switch is grounded. A third terminal of the first electronic switch is connected to a first terminal of the second electronic switch, and connected to the +3.3V dual power supply through a second resistor. A second terminal of the second electronic switch is connected to the +3.3V dual power supply. A third terminal of the second electronic switch is connected to a PCI-E slot.

Abstract: A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump.

Abstract: A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump.