Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Abstract: A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Abstract: A process for depositing, through plasma enhanced chemical vapor deposition, inorganic films having low dielectric constant is disclosed. After deposition under low power for a few seconds the power is raised to high for a few seconds, deposition of the film continuing to alternate between low and high power modes until the total desired thickness is reached. Additionally, for the deposition of materials such as black diamond, oxygen is added to the plasma during the high power phase (and removed during the low power phase). We have found that films deposited in this way have low flat band voltages, close to zero, and are, in general, more robust than films deposited according to prior art methods. In particular, these films are free of the cracking problems often encountered during chemical mechanical polishing of films of this type during the formation of damascene structures.

Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Abstract: In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.

Abstract: A layer of low k dielectric is formed on a substrate having a conducting electrode formed therein. A via hole is formed in the low k dielectric exposing the conducting electrode. A thin layer of amorphous silicon is deposited on the layer of low k dielectric and on the sidewalls and bottom of a via hole. A layer of resist is then formed and patterned with a trench pattern. A trench is etched in the layer of low k dielectric directly over the via hole using the patterned layer of resist. The patterned layer of resist is then stripped and the trench and via hole are filled with conducting material. The layer of amorphous silicon prevents amine radicals, NHx, which can be released from the low k dielectric, especially during the via hole etching, from interacting with the resist and forming resist scum resulting in via poisoning.

Abstract: A method for in-situ cleaning a polishing pad and a wafer surface simultaneously during copper chemical mechanical polishing and an apparatus for carrying out such method are disclosed. The method is carried out by dispensing an acid-containing solution onto a top surface of a polishing pad while the wafer is rotated against the polishing pad without any slurry solution being dispensed. The acid-containing solution may be advantageously formed by diluting an acid such as citric acid, HCOOH, CH3COOH, HNO3, H2SO4 and HF to a concentration of less than 10 wt. % acid, preferably less than 5 wt. % acid, and more preferably less than 1 wt. % acid. The acid-containing solution may be dispensed onto a top surface of the polishing pad for a time period between about 30 sec. and about 300 sec.

Abstract: Within a method for forming a dielectric layer within a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a carbon doped silicon containing dielectric layer. There is then treated the carbon doped silicon containing dielectric layer with an oxidizing plasma to form from the carbon doped silicon containing dielectric layer an oxidizing plasma treated carbon doped silicon containing dielectric layer.

Abstract: Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.

Abstract: A method of fabricating a CVD low-k SiOCN material. The first embodiment comprising the following steps. MeSiH3, N2O, and N2 are reacted at a molar ratio of from about 1:5:10 to 1:10:15, at a plasma power from about 0 to 400 W to deposit a final deposited film. The final deposited film is treated to stabilize the final deposited film to form a CVD low-k SiOCN material. The second embodiment comprising the following steps. A starting mixture of MeSiH3, SiH4, N2O, and N2 is reacted at a molar ratio of from about 1:1:5:10 to 1:5:10:15, in a plasma in a helium carrier gas at a plasma power from about 0 to 400 W to deposit a CVD low-k SiOCN material.

Abstract: Black diamond films, deposited using PECVD at low substrate temperatures, have been effectively stabilized by immersing them in de-ionized water at a temperature of about 90° C. for about 20 minutes or in a hydrogen peroxide solution (typically at a concentration of 10%) for about 60 minutes. Since it has been observed that the dielectric constant of the stabilized film increases with both immersion time and/or peroxide concentration, this effect may be used as a means for adjusting the dielectric constant of a black diamond film. Standard analytical techniques confirm that these low temperature stabilized films have electrical properties that are at least as good as those of films stabilized using high temperature heat treatments.

Abstract: A type of musical rotating luminous device is composed of a base, retarding device, rotating stand, outer shell and a luminous device. It utilizes the battery's power within the base to make the motor drive the retarding device. Within the said rotating stand, a central shaft is connected to a retarding device. At one end of the central shaft, a drive sprocket is fitted on, while the other end is attached to a stand's rotary wheel. Additionally, in each corner of a containment space, a plurality of shaft rods pass through the stand. At the other end of the shaft rods, drive sprockets of different diameter sizes are attached. Between the shaft rods and the central shaft the drive sprockets engage a plurality of driven sprockets, transferring the driven force. Furthermore, the outer shell houses the said base, retarding device and rotating stand. When in use, and due to the different diameter sizes of the drive sprockets, the central shaft and the shaft rods will spin at different speeds.